From patchwork Fri Jan 6 04:14:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 9500023 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E2FA7606B5 for ; Fri, 6 Jan 2017 04:16:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D89B92841A for ; Fri, 6 Jan 2017 04:16:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CD25528482; Fri, 6 Jan 2017 04:16:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 317E92841A for ; Fri, 6 Jan 2017 04:16:45 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cPLxJ-0006Jf-Gb; Fri, 06 Jan 2017 04:16:41 +0000 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cPLws-0005fn-Cg for linux-arm-kernel@lists.infradead.org; Fri, 06 Jan 2017 04:16:19 +0000 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 3CA7F886C1; Fri, 6 Jan 2017 17:15:54 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail; t=1483676154; bh=CNI/M/tUPzICQcX36tRBR+pHDKHwr+O9wDBX/NQqNBQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HxJnh2+/M3fDIFZTO9jLVaPHLL2LHdcbZLG/IYlsUByYfzgDAnahEEM/P6JWlnAa5 xHBj21W81SRnvMrk9ho7qfYl6e3DeAPH8mRguTNtgCkoee3KLTsAQaIzFtrhJdAP10 PL+lOc9eVai6G6t+/7XEhPUNbCOtU8kaPgnnwyxQ= Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 6, 8438) id ; Fri, 06 Jan 2017 17:15:53 +1300 Received: from chrisp-dl.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 1B72513EC2D; Fri, 6 Jan 2017 17:15:53 +1300 (NZDT) Received: by chrisp-dl.atlnz.lc (Postfix, from userid 1030) id AFC511E0BBD; Fri, 6 Jan 2017 17:15:53 +1300 (NZDT) From: Chris Packham To: linux-arm-kernel@lists.infradead.org Subject: [PATCHv3 2/5] arm: mvebu: support for SMP on 98DX3336 SoC Date: Fri, 6 Jan 2017 17:14:59 +1300 Message-Id: <20170106041517.9589-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.11.0.24.ge6920cf In-Reply-To: <20170106041517.9589-1-chris.packham@alliedtelesis.co.nz> References: <20170105033641.6212-1-chris.packham@alliedtelesis.co.nz> <20170106041517.9589-1-chris.packham@alliedtelesis.co.nz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170105_201614_996695_23536681 X-CRM114-Status: GOOD ( 18.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Andrew Lunn , Florian Fainelli , Jayachandran C , Jason Cooper , Geert Uytterhoeven , devicetree@vger.kernel.org, Juri Lelli , Magnus Damm , Russell King , Rob Herring , linux-kernel@vger.kernel.org, Chris Packham , Chris Brand , Sudeep Holla , Gregory Clement , Lorenzo Pieralisi , Thierry Reding , Stephen Boyd , Sebastian Hesselbarth MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Compared to the armada-xp the 98DX3336 uses different registers to set the boot address for the secondary CPU so a new enable-method is needed. This will only work if the machine definition doesn't define an overall smp_ops because there is not currently a way of overriding this from the device tree if it is set in the machine definition. Signed-off-by: Chris Packham Acked-by: Rob Herring --- Changes in v2: - Document new enable-method value - Correct some references from 98DX4521 to 98DX3236 Changes in v3: - Simplify mv98dx3236_resume_init by using of_io_request_and_map() Documentation/devicetree/bindings/arm/cpus.txt | 1 + .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 18 ++++++++ arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/common.h | 1 + arch/arm/mach-mvebu/platsmp.c | 43 ++++++++++++++++++ arch/arm/mach-mvebu/pmsu-98dx3236.c | 52 ++++++++++++++++++++++ 6 files changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt create mode 100644 arch/arm/mach-mvebu/pmsu-98dx3236.c diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index a1bcfeed5f24..3c2fd72d0bf9 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -202,6 +202,7 @@ nodes to be present and contain the properties described below. "marvell,armada-380-smp" "marvell,armada-390-smp" "marvell,armada-xp-smp" + "marvell,98dx3236-smp" "mediatek,mt6589-smp" "mediatek,mt81xx-tz-smp" "qcom,gcc-msm8660" diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt new file mode 100644 index 000000000000..8082ba872edd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt @@ -0,0 +1,18 @@ +Resume Control +-------------- +Available on Marvell SOCs: 98DX3336 and 98DX4251 + +Required properties: + +- compatible: must be "marvell,98dx3336-resume-ctrl" + +- reg: Should contain resume control registers location and length + +Example: + +resume@20980 { + compatible = "marvell,98dx3336-resume-ctrl"; + reg = <0x20980 0x10>; +}; + + diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 6c6497e80a7b..2a2dd8324fb8 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_MACH_MVEBU_ANY) += system-controller.o mvebu-soc-id.o ifeq ($(CONFIG_MACH_MVEBU_V7),y) obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o +obj-y += pmsu-98dx3236.o obj-$(CONFIG_PM) += pm.o pm-board.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h index 6b775492cfad..099dabf23461 100644 --- a/arch/arm/mach-mvebu/common.h +++ b/arch/arm/mach-mvebu/common.h @@ -27,4 +27,5 @@ void __iomem *mvebu_get_scu_base(void); int mvebu_pm_suspend_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd)); +void mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr); #endif diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index 46c742d3bd41..3c9ab9a008ad 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -182,5 +182,48 @@ const struct smp_operations armada_xp_smp_ops __initconst = { #endif }; +static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + int ret, hw_cpu; + + pr_info("Booting CPU %d\n", cpu); + + hw_cpu = cpu_logical_map(cpu); + set_secondary_cpu_clock(hw_cpu); + mv98dx3236_resume_set_cpu_boot_addr(hw_cpu, + armada_xp_secondary_startup); + + /* + * This is needed to wake up CPUs in the offline state after + * using CPU hotplug. + */ + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + + /* + * This is needed to take secondary CPUs out of reset on the + * initial boot. + */ + ret = mvebu_cpu_reset_deassert(hw_cpu); + if (ret) { + pr_warn("unable to boot CPU: %d\n", ret); + return ret; + } + + return 0; +} + +struct smp_operations mv98dx3236_smp_ops __initdata = { + .smp_init_cpus = armada_xp_smp_init_cpus, + .smp_prepare_cpus = armada_xp_smp_prepare_cpus, + .smp_boot_secondary = mv98dx3236_boot_secondary, + .smp_secondary_init = armada_xp_secondary_init, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = armada_xp_cpu_die, + .cpu_kill = armada_xp_cpu_kill, +#endif +}; + CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp", &armada_xp_smp_ops); +CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp", + &mv98dx3236_smp_ops); diff --git a/arch/arm/mach-mvebu/pmsu-98dx3236.c b/arch/arm/mach-mvebu/pmsu-98dx3236.c new file mode 100644 index 000000000000..1052674dd439 --- /dev/null +++ b/arch/arm/mach-mvebu/pmsu-98dx3236.c @@ -0,0 +1,52 @@ +/** + * CPU resume support for 98DX3236 internal CPU (a.k.a. MSYS). + */ + +#define pr_fmt(fmt) "mv98dx3236-resume: " fmt + +#include +#include +#include +#include +#include "common.h" + +static void __iomem *mv98dx3236_resume_base; +#define MV98DX3236_CPU_RESUME_CTRL_OFFSET 0x08 +#define MV98DX3236_CPU_RESUME_ADDR_OFFSET 0x04 + +static const struct of_device_id of_mv98dx3236_resume_table[] = { + {.compatible = "marvell,98dx3336-resume-ctrl",}, + { /* end of list */ }, +}; + +void mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr) +{ + WARN_ON(hw_cpu != 1); + + writel(0, mv98dx3236_resume_base + MV98DX3236_CPU_RESUME_CTRL_OFFSET); + writel(virt_to_phys(boot_addr), mv98dx3236_resume_base + + MV98DX3236_CPU_RESUME_ADDR_OFFSET); +} + +static int __init mv98dx3236_resume_init(void) +{ + struct device_node *np; + void __iomem *base; + + np = of_find_matching_node(NULL, of_mv98dx3236_resume_table); + if (!np) + return 0; + + base = of_io_request_and_map(np, 0, of_node_full_name(np)); + if (IS_ERR(base)) { + pr_err("unable to map registers\n"); + of_node_put(np); + return PTR_ERR(mv98dx3236_resume_base); + } + + mv98dx3236_resume_base = base; + of_node_put(np); + return 0; +} + +early_initcall(mv98dx3236_resume_init);