From patchwork Wed Jan 18 20:38:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: afzal mohammed X-Patchwork-Id: 9524749 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5EC5F60113 for ; Wed, 18 Jan 2017 20:38:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D989285F0 for ; Wed, 18 Jan 2017 20:38:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4125528624; Wed, 18 Jan 2017 20:38:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B9482285F0 for ; Wed, 18 Jan 2017 20:38:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cTx0H-000309-Tk; Wed, 18 Jan 2017 20:38:45 +0000 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cTx0F-0002tL-8V for linux-arm-kernel@lists.infradead.org; Wed, 18 Jan 2017 20:38:44 +0000 Received: by mail-pg0-x241.google.com with SMTP id 204so2196593pge.2 for ; Wed, 18 Jan 2017 12:38:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dPzo9Np+zm7FvnojeL/2fyLslQndoCjPmgybzWPt/c4=; b=n6dRq7UUcz+hWxrx11ppLKarDqC7at8t0VyyO0X+473MtM6NRjNoYEz/XKzU0lVCJg sAgk132pi8nu6aRee8Z7sfEWmcNIzCwKT6/dRxaOBHwYpnJyrHUDL6rCXRqYCYRhkvqC OAo+4Tx2PpqPqj/r9y38+3di8r60iztKvkoqFO8b0djBiNLURApN/mFInBCyfl72tPFQ P4+ekjmx6c3mcaPeHgAYfS9jcGsqkUHaidWYC7UfIMz6h4j2TC+wEHtb2I5RfxCcv0Gq dMHUnYf3Qob/pOGjfVOsvw+q7pPSaiUanXw1bBwPlK0jThynAsX0ffu140um7CheINFF K0MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dPzo9Np+zm7FvnojeL/2fyLslQndoCjPmgybzWPt/c4=; b=Hp5zaXb3n5R/4wpA/rVebX+D2kPPhHQwDbtumgUKNlQCsw798pbF67qkc89chaWp4M WWDQ5x7PS115ai9/M9mjxJMU+WstIij9OLsAq+4U+yyIJ3T2iKluyukQ9SL1fYiuPYMI DHr5sIo/JVgHT8DzydjyqcKAIwWK00T020ZxjqDI3x1qqXieAAdzQreOmGR8Pdl7G3g1 XS/s/HiLvoxmfD/j7cgV+HnFQ7pVTpT2bHYViBgfcqGd+i4iLvxPm++LX4t7DSFNLstQ 5fWuIg0yVoXeUA4L0Uuy/G1rVUiGnCKrPTVIO/bUpk0Y9mBDxXASyCF95RbbWlIZhyow 2ycQ== X-Gm-Message-State: AIkVDXIVnsTDrRvkN4fcdCi5q45A0e0gIIKWJkcT2FFIN3GFRI7DsNwnWocMfEbX9eXQeQ== X-Received: by 10.98.84.193 with SMTP id i184mr5940872pfb.27.1484771902628; Wed, 18 Jan 2017 12:38:22 -0800 (PST) Received: from localhost.localdomain ([49.203.213.22]) by smtp.gmail.com with ESMTPSA id k76sm2795325pfg.42.2017.01.18.12.38.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Jan 2017 12:38:22 -0800 (PST) From: afzal mohammed To: Russell King - ARM Linux Subject: [PATCH 2/4] ARM: nommu: dynamic exception base address setting Date: Thu, 19 Jan 2017 02:08:07 +0530 Message-Id: <20170118203807.6467-1-afzal.mohd.ma@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170118203525.6246-1-afzal.mohd.ma@gmail.com> References: <20170118203525.6246-1-afzal.mohd.ma@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170118_123843_333143_3ED3B9F7 X-CRM114-Status: GOOD ( 17.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vladimir Murzin , afzal mohammed , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP No-MMU dynamic exception base address configuration on CP15 processors. In the case of low vectors, decision based on whether security extensions are enabled & whether remap vectors to RAM CONFIG option is selected. For no-MMU without CP15, current default value of 0x0 is retained. Signed-off-by: afzal mohammed --- arch/arm/mm/nommu.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 62 insertions(+), 2 deletions(-) diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 2740967727e2..db8e784f20f3 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -22,6 +23,8 @@ #include "mm.h" +unsigned long vectors_base; + #ifdef CONFIG_ARM_MPU struct mpu_rgn_info mpu_rgn_info; @@ -278,15 +281,72 @@ static void sanity_check_meminfo_mpu(void) {} static void __init mpu_setup(void) {} #endif /* CONFIG_ARM_MPU */ +#ifdef CONFIG_CPU_CP15 +#ifdef CONFIG_CPU_HIGH_VECTOR +static unsigned long __init setup_vectors_base(void) +{ + unsigned long reg = get_cr(); + + set_cr(reg | CR_V); + return 0xffff0000; +} +#else /* CONFIG_CPU_HIGH_VECTOR */ +/* + * ID_PRF1 bits (CP#15 ID_PFR1) + */ +#define ID_PFR1_SE (0x3 << 4) /* Security extension enable bits */ + +/* Read processor feature register ID_PFR1 */ +static unsigned long get_id_pfr1(void) +{ + unsigned long val; + + asm("mrc p15, 0, %0, c0, c1, 1" : "=r" (val) : : "cc"); + return val; +} + +/* Write exception base address to VBAR */ +static void set_vbar(unsigned long val) +{ + asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc"); +} + +static bool __init security_extensions_enabled(void) +{ + return !!(get_id_pfr1() & ID_PFR1_SE); +} + +static unsigned long __init setup_vectors_base(void) +{ + unsigned long base = 0, reg = get_cr(); + + set_cr(reg & ~CR_V); + if (security_extensions_enabled()) { + if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) + base = CONFIG_DRAM_BASE; + set_vbar(base); + } else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) { + if (CONFIG_DRAM_BASE != 0) + pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n"); + } + + return base; +} +#endif /* CONFIG_CPU_HIGH_VECTOR */ +#endif /* CONFIG_CPU_CP15 */ + void __init arm_mm_memblock_reserve(void) { #ifndef CONFIG_CPU_V7M +#ifdef CONFIG_CPU_CP15 + vectors_base = setup_vectors_base(); +#endif /* * Register the exception vector page. * some architectures which the DRAM is the exception vector to trap, * alloc_page breaks with error, although it is not NULL, but "0." */ - memblock_reserve(CONFIG_VECTORS_BASE, 2 * PAGE_SIZE); + memblock_reserve(vectors_base, 2 * PAGE_SIZE); #else /* ifndef CONFIG_CPU_V7M */ /* * There is no dedicated vector page on V7-M. So nothing needs to be @@ -310,7 +370,7 @@ void __init sanity_check_meminfo(void) */ void __init paging_init(const struct machine_desc *mdesc) { - early_trap_init((void *)CONFIG_VECTORS_BASE); + early_trap_init((void *)vectors_base); mpu_setup(); bootmem_init(); }