From patchwork Fri Jan 27 03:25:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 9540571 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 89A7560429 for ; Fri, 27 Jan 2017 03:27:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7815820855 for ; Fri, 27 Jan 2017 03:27:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6B4E727F8F; Fri, 27 Jan 2017 03:27:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, T_DKIM_INVALID autolearn=no version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BBEB920855 for ; Fri, 27 Jan 2017 03:27:43 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cWxCQ-0001im-DQ; Fri, 27 Jan 2017 03:27:42 +0000 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cWxBg-00011X-LB for linux-arm-kernel@lists.infradead.org; Fri, 27 Jan 2017 03:26:58 +0000 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 37BC4886C1; Fri, 27 Jan 2017 16:26:07 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail; t=1485487567; bh=c447CUrN90scYc9BVKbiVlXCltPT7RSy96O4k9bW2xg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=k+aQaeoccGB8rk09MOBKtcE++zccv4fpfu0J0pBFRqR4VV5PiYSYCNIRZjurhrY1b TQaiXI/nzU5y42VyiwcEWsiiAQhSfd6a5NiQ1U4qjipUbUU/2xEcMCWWfFgDvSlglg 1o3/6DAB6pzf3d93BJLn9Bny07R9T+LuawvGzEhk= Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 6, 8438) id ; Fri, 27 Jan 2017 16:26:07 +1300 Received: from chrisp-dl.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 54D7513F120; Fri, 27 Jan 2017 16:26:06 +1300 (NZDT) Received: by chrisp-dl.atlnz.lc (Postfix, from userid 1030) id 6FB121E1DE0; Fri, 27 Jan 2017 16:26:06 +1300 (NZDT) From: Chris Packham To: linux@armlinux.org.uk, linux-arm-kernel@lists.infradead.org Subject: [PATCHv5 2/5] arm: mvebu: support for SMP on 98DX3336 SoC Date: Fri, 27 Jan 2017 16:25:43 +1300 Message-Id: <20170127032546.14657-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.11.0.24.ge6920cf In-Reply-To: <20170127032546.14657-1-chris.packham@alliedtelesis.co.nz> References: <20170127032546.14657-1-chris.packham@alliedtelesis.co.nz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170126_192657_043546_2D38B4FF X-CRM114-Status: GOOD ( 18.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Andrew Lunn , Jason Cooper , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Chris Packham , Gregory Clement , Sebastian Hesselbarth MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Compared to the armada-xp the 98DX3336 uses different registers to set the boot address for the secondary CPU so a new enable-method is needed. This will only work if the machine definition doesn't define an overall smp_ops because there is not currently a way of overriding this from the device tree if it is set in the machine definition. Signed-off-by: Chris Packham Acked-by: Rob Herring --- Notes: Changes in v2: - Document new enable-method value - Correct some references from 98DX4521 to 98DX3236 Changes in v3: - Simplify mv98dx3236_resume_init by using of_io_request_and_map() Changes in v4: - integrate changes into platsmp.c instead of new init call - avoid duplicated code. - fix error return - Collect ack from Rob Changes in v5: - Remove useless casts (thanks to Stephen Boyd) Documentation/devicetree/bindings/arm/cpus.txt | 1 + .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 16 ++++ arch/arm/mach-mvebu/platsmp.c | 86 ++++++++++++++++++++++ 3 files changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index a1bcfeed5f24..3c2fd72d0bf9 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -202,6 +202,7 @@ nodes to be present and contain the properties described below. "marvell,armada-380-smp" "marvell,armada-390-smp" "marvell,armada-xp-smp" + "marvell,98dx3236-smp" "mediatek,mt6589-smp" "mediatek,mt81xx-tz-smp" "qcom,gcc-msm8660" diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt new file mode 100644 index 000000000000..26eb9d3aa630 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt @@ -0,0 +1,16 @@ +Resume Control +-------------- +Available on Marvell SOCs: 98DX3336 and 98DX4251 + +Required properties: + +- compatible: must be "marvell,98dx3336-resume-ctrl" + +- reg: Should contain resume control registers location and length + +Example: + +resume@20980 { + compatible = "marvell,98dx3336-resume-ctrl"; + reg = <0x20980 0x10>; +}; diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index 46c742d3bd41..a5b464497e1a 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -184,3 +184,89 @@ const struct smp_operations armada_xp_smp_ops __initconst = { CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp", &armada_xp_smp_ops); + +struct resume_controller { + u32 resume_control; + u32 resume_boot_addr; +}; + +static const struct resume_controller mv98dx3336_resume_controller = { + .resume_control = 0x08, + .resume_boot_addr = 0x04, +}; + +static const struct of_device_id of_mv98dx3236_resume_table[] = { + { + .compatible = "marvell,98dx3336-resume-ctrl", + .data = &mv98dx3336_resume_controller, + }, + { /* end of list */ }, +}; + +static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr) +{ + const struct of_device_id *match; + struct device_node *np; + void __iomem *base; + const struct resume_controller *rc; + + WARN_ON(hw_cpu != 1); + + np = of_find_matching_node_and_match(NULL, of_mv98dx3236_resume_table, + &match); + if (!np) + return -ENODEV; + + base = of_io_request_and_map(np, 0, of_node_full_name(np)); + rc = match->data; + of_node_put(np); + if (IS_ERR(base)) + return PTR_ERR(base); + + writel(0, base + rc->resume_control); + writel(virt_to_phys(boot_addr), base + rc->resume_boot_addr); + + return 0; +} + +static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + int ret, hw_cpu; + + hw_cpu = cpu_logical_map(cpu); + set_secondary_cpu_clock(hw_cpu); + mv98dx3236_resume_set_cpu_boot_addr(hw_cpu, + armada_xp_secondary_startup); + + /* + * This is needed to wake up CPUs in the offline state after + * using CPU hotplug. + */ + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + + /* + * This is needed to take secondary CPUs out of reset on the + * initial boot. + */ + ret = mvebu_cpu_reset_deassert(hw_cpu); + if (ret) { + pr_warn("unable to boot CPU: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct smp_operations mv98dx3236_smp_ops __initconst = { + .smp_init_cpus = armada_xp_smp_init_cpus, + .smp_prepare_cpus = armada_xp_smp_prepare_cpus, + .smp_boot_secondary = mv98dx3236_boot_secondary, + .smp_secondary_init = armada_xp_secondary_init, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = armada_xp_cpu_die, + .cpu_kill = armada_xp_cpu_kill, +#endif +}; + +CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp", + &mv98dx3236_smp_ops);