| Message ID | 20170215180159.11359-1-cov@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 02/15/2017 12:01 PM, Christopher Covington wrote: > Signed-off-by: Christopher Covington <cov@codeaurora.org> > Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Timur Tabi <timur@codeaurora.org> It would great if we could get this into 4.11. As crazy it sounds, it is the only critical patch in 4.11 that we need for our platform.
On Wed, Feb 15, 2017 at 01:01:59PM -0500, Christopher Covington wrote: > The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a > custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the > BUSY bit in the Flag Register gets stuck as 1, erratum 44 for both 2432v1 > and 2400v1 SoCs.Checking that the Transmit FIFO Empty (TXFE) bit is 0, > instead of checking that the BUSY bit is 1, works around the issue. > > To facilitate this substitution of flags and values, introduce > vendor-specific inversion of Feature Register bits when UART AMBA Port > (UAP) data is available. For the earlycon case, prior to UAP availability, > implement alternative putc and early_write functions. > > Similar to what how ARMv8 ACPI PCI quirks are detected during MCFG parsing, > check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI > table to determine if the current platform is known to be affected by the > erratum. > > Signed-off-by: Christopher Covington <cov@codeaurora.org> > Acked-by: Russell King <rmk+kernel@armlinux.org.uk> > --- > Since v2: Formatting and other improvements per Timur's suggestions > Due to known (although trivial) conflicts in silicon-errata.txt, based on > http://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core > --- > Documentation/arm64/silicon-errata.txt | 2 ++ > drivers/acpi/spcr.c | 23 ++++++++++++ > drivers/tty/serial/amba-pl011.c | 66 ++++++++++++++++++++++++++++++---- > 3 files changed, 84 insertions(+), 7 deletions(-) > > diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt > index a71b8095dbd8..bc3d086bc624 100644 > --- a/Documentation/arm64/silicon-errata.txt > +++ b/Documentation/arm64/silicon-errata.txt > @@ -68,3 +68,5 @@ stable kernels. > | | | | | > | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | > | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | > +| Qualcomm Tech. | QDF2432v1 UART | SoC E44 | N/A | > +| Qualcomm Tech. | QDF2400v1 UART | SoC E44 | N/A | > diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c > index b8019c4c1d38..2b5d0fac81f0 100644 > --- a/drivers/acpi/spcr.c > +++ b/drivers/acpi/spcr.c > @@ -16,6 +16,26 @@ > #include <linux/kernel.h> > #include <linux/serial_core.h> > > +/* > + * Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit. > + * Detect them by examining the OEM fields in the SPCR header, similiar to PCI > + * quirk detection in pci_mcfg.c. > + */ > +static bool qdf2400_erratum_44_present(struct acpi_table_header *h) > +{ > + if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE)) > + return false; > + > + if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE)) > + return true; > + > + if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) && > + h->oem_revision == 0) > + return true; > + > + return false; > +} > + > /** > * parse_spcr() - parse ACPI SPCR table and add preferred console > * > @@ -93,6 +113,9 @@ int __init parse_spcr(bool earlycon) > goto done; > } > > + if (qdf2400_erratum_44_present(&table->header)) > + uart = "qdf2400_e44"; > + This addresses my concern with using the MIDR; thanks for respinning this. FWIW: Acked-by: Mark Rutland <mark.rutland@arm.com> It might be best to split the silicon-errata doc into a separate patch. That can go via the arm64 tree without conflict whiel the driver patch can go via the tty tree. Thanks, Mark.
On Wed, Feb 15, 2017 at 07:50:27PM +0000, Mark Rutland wrote: > On Wed, Feb 15, 2017 at 01:01:59PM -0500, Christopher Covington wrote: > > The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a > > custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the > > BUSY bit in the Flag Register gets stuck as 1, erratum 44 for both 2432v1 > > and 2400v1 SoCs.Checking that the Transmit FIFO Empty (TXFE) bit is 0, > > instead of checking that the BUSY bit is 1, works around the issue. > > > > To facilitate this substitution of flags and values, introduce > > vendor-specific inversion of Feature Register bits when UART AMBA Port > > (UAP) data is available. For the earlycon case, prior to UAP availability, > > implement alternative putc and early_write functions. > > > > Similar to what how ARMv8 ACPI PCI quirks are detected during MCFG parsing, > > check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI > > table to determine if the current platform is known to be affected by the > > erratum. > > > > Signed-off-by: Christopher Covington <cov@codeaurora.org> > > Acked-by: Russell King <rmk+kernel@armlinux.org.uk> > > --- > > Since v2: Formatting and other improvements per Timur's suggestions > > Due to known (although trivial) conflicts in silicon-errata.txt, based on > > http://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core > > --- > > Documentation/arm64/silicon-errata.txt | 2 ++ > > drivers/acpi/spcr.c | 23 ++++++++++++ > > drivers/tty/serial/amba-pl011.c | 66 ++++++++++++++++++++++++++++++---- > > 3 files changed, 84 insertions(+), 7 deletions(-) > > > > diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt > > index a71b8095dbd8..bc3d086bc624 100644 > > --- a/Documentation/arm64/silicon-errata.txt > > +++ b/Documentation/arm64/silicon-errata.txt > > @@ -68,3 +68,5 @@ stable kernels. > > | | | | | > > | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | > > | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | > > +| Qualcomm Tech. | QDF2432v1 UART | SoC E44 | N/A | > > +| Qualcomm Tech. | QDF2400v1 UART | SoC E44 | N/A | > > diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c > > index b8019c4c1d38..2b5d0fac81f0 100644 > > --- a/drivers/acpi/spcr.c > > +++ b/drivers/acpi/spcr.c > > @@ -16,6 +16,26 @@ > > #include <linux/kernel.h> > > #include <linux/serial_core.h> > > > > +/* > > + * Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit. > > + * Detect them by examining the OEM fields in the SPCR header, similiar to PCI > > + * quirk detection in pci_mcfg.c. > > + */ > > +static bool qdf2400_erratum_44_present(struct acpi_table_header *h) > > +{ > > + if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE)) > > + return false; > > + > > + if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE)) > > + return true; > > + > > + if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) && > > + h->oem_revision == 0) > > + return true; > > + > > + return false; > > +} > > + > > /** > > * parse_spcr() - parse ACPI SPCR table and add preferred console > > * > > @@ -93,6 +113,9 @@ int __init parse_spcr(bool earlycon) > > goto done; > > } > > > > + if (qdf2400_erratum_44_present(&table->header)) > > + uart = "qdf2400_e44"; > > + > > This addresses my concern with using the MIDR; thanks for respinning > this. FWIW: > > Acked-by: Mark Rutland <mark.rutland@arm.com> > > It might be best to split the silicon-errata doc into a separate patch. > That can go via the arm64 tree without conflict whiel the driver patch > can go via the tty tree. Well, I can't take this as-is because I get conflicts in my tty tree with the doc, and with the driver itself: checking file Documentation/arm64/silicon-errata.txt Hunk #1 FAILED at 68. 1 out of 1 hunk FAILED checking file drivers/acpi/spcr.c checking file drivers/tty/serial/amba-pl011.c Hunk #5 FAILED at 2370. 1 out of 8 hunks FAILED I have no idea what the driver conflict is, what branch was this made against? thanks, greg k-h
On 02/15/2017 03:07 PM, Greg Kroah-Hartman wrote: > On Wed, Feb 15, 2017 at 07:50:27PM +0000, Mark Rutland wrote: >> On Wed, Feb 15, 2017 at 01:01:59PM -0500, Christopher Covington wrote: >>> Due to known (although trivial) conflicts in silicon-errata.txt, based on >>> http://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core >> It might be best to split the silicon-errata doc into a separate patch. >> That can go via the arm64 tree without conflict whiel the driver patch >> can go via the tty tree. > > Well, I can't take this as-is because I get conflicts in my tty tree > with the doc, and with the driver itself: > > checking file Documentation/arm64/silicon-errata.txt > Hunk #1 FAILED at 68. > 1 out of 1 hunk FAILED > checking file drivers/acpi/spcr.c > checking file drivers/tty/serial/amba-pl011.c > Hunk #5 FAILED at 2370. > 1 out of 8 hunks FAILED > > I have no idea what the driver conflict is, what branch was this made > against? I'll make the split Mark suggested in v4, basing driver changes on gregkh/tty tty-next unless someone suggests otherwise. (FWIW the previous base was arm64/linux.git for-next/core.) Thanks, Cov
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index a71b8095dbd8..bc3d086bc624 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -68,3 +68,5 @@ stable kernels. | | | | | | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | +| Qualcomm Tech. | QDF2432v1 UART | SoC E44 | N/A | +| Qualcomm Tech. | QDF2400v1 UART | SoC E44 | N/A | diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c index b8019c4c1d38..2b5d0fac81f0 100644 --- a/drivers/acpi/spcr.c +++ b/drivers/acpi/spcr.c @@ -16,6 +16,26 @@ #include <linux/kernel.h> #include <linux/serial_core.h> +/* + * Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit. + * Detect them by examining the OEM fields in the SPCR header, similiar to PCI + * quirk detection in pci_mcfg.c. + */ +static bool qdf2400_erratum_44_present(struct acpi_table_header *h) +{ + if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE)) + return false; + + if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE)) + return true; + + if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) && + h->oem_revision == 0) + return true; + + return false; +} + /** * parse_spcr() - parse ACPI SPCR table and add preferred console * @@ -93,6 +113,9 @@ int __init parse_spcr(bool earlycon) goto done; } + if (qdf2400_erratum_44_present(&table->header)) + uart = "qdf2400_e44"; + snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype, table->serial_port.address, baud_rate); diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index d4171d71a258..fbd1ea251854 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -97,6 +97,7 @@ struct vendor_data { unsigned int fr_dsr; unsigned int fr_cts; unsigned int fr_ri; + unsigned int inv_fr; bool access_32b; bool oversampling; bool dma_threshold; @@ -141,6 +142,30 @@ static struct vendor_data vendor_sbsa = { .fixed_options = true, }; +/* + * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as + * occasionally getting stuck as 1. To avoid the potential for a hang, check + * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART + * implementations, so only do so if an affected platform is detected in + * parse_spcr(). + */ +static bool qdf2400_e44_present = false; + +static struct vendor_data vendor_qdt_qdf2400_e44 = { + .reg_offset = pl011_std_offsets, + .fr_busy = UART011_FR_TXFE, + .fr_dsr = UART01x_FR_DSR, + .fr_cts = UART01x_FR_CTS, + .fr_ri = UART011_FR_RI, + .inv_fr = UART011_FR_TXFE, + .access_32b = true, + .oversampling = false, + .dma_threshold = false, + .cts_event_workaround = false, + .always_enabled = true, + .fixed_options = true, +}; + static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { [REG_DR] = UART01x_DR, [REG_ST_DMAWM] = ST_UART011_DMAWM, @@ -1518,7 +1543,10 @@ static unsigned int pl011_tx_empty(struct uart_port *port) { struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); - unsigned int status = pl011_read(uap, REG_FR); + + /* Allow feature register bits to be inverted to work around errata */ + unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; + return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; } @@ -2215,10 +2243,12 @@ pl011_console_write(struct console *co, const char *s, unsigned int count) uart_console_write(&uap->port, s, count, pl011_console_putchar); /* - * Finally, wait for transmitter to become empty - * and restore the TCR + * Finally, wait for transmitter to become empty and restore the + * TCR. Allow feature register bits to be inverted to work around + * errata. */ - while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) + while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) + & uap->vendor->fr_busy) cpu_relax(); if (!uap->vendor->always_enabled) pl011_write(old_cr, uap, REG_CR); @@ -2340,8 +2370,12 @@ static int __init pl011_console_match(struct console *co, char *name, int idx, resource_size_t addr; int i; - if (strcmp(name, "pl011") != 0) + if (strcmp(name, "qdf2400_e44") == 0) { + pr_info_once("UART: Working around QDF2400 SoC erratum 44"); + qdf2400_e44_present = true; + } else if (strcmp(name, "pl011") != 0) { return -ENODEV; + } if (uart_parse_earlycon(options, &iotype, &addr, &options)) return -ENODEV; @@ -2383,6 +2417,22 @@ static struct console amba_console = { #define AMBA_CONSOLE (&amba_console) +static void qdf2400_e44_putc(struct uart_port *port, int c) +{ + while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) + cpu_relax(); + writel(c, port->membase + UART01x_DR); + while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) + cpu_relax(); +} + +static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n) +{ + struct earlycon_device *dev = con->data; + + uart_console_write(&dev->port, s, n, qdf2400_e44_putc); +} + static void pl011_putc(struct uart_port *port, int c) { while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) @@ -2408,7 +2458,8 @@ static int __init pl011_early_console_setup(struct earlycon_device *device, if (!device->port.membase) return -ENODEV; - device->con->write = pl011_early_write; + device->con->write = qdf2400_e44_present ? + qdf2400_e44_early_write : pl011_early_write; return 0; } OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); @@ -2645,7 +2696,8 @@ static int sbsa_uart_probe(struct platform_device *pdev) uap->port.irq = ret; uap->reg_offset = vendor_sbsa.reg_offset; - uap->vendor = &vendor_sbsa; + uap->vendor = qdf2400_e44_present ? + &vendor_qdt_qdf2400_e44 : &vendor_sbsa; uap->fifosize = 32; uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM; uap->port.ops = &sbsa_uart_pops;