From patchwork Thu Feb 16 16:17:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 9577695 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D100A6049F for ; Thu, 16 Feb 2017 16:20:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C18D528632 for ; Thu, 16 Feb 2017 16:20:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B493228635; Thu, 16 Feb 2017 16:20:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 45E0828634 for ; Thu, 16 Feb 2017 16:20:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=A7FzoPUrQ/650iL7Gs2E0NBywN4Cyuy7NSdEIot+JV4=; b=Ln69TFCW8xQkMv4jJvcJ8oLjdW w/S108AK8kR0lQhOQnOGCdxHhTFEFyxC4z32AS7hZpcjwnUHrUM3FcKDW/XvK99Ss3+SpA7rQm6jy wJp/dMSZGuInmHqhF3swU60zO0W2yvCjT4CwgALuDk5OlIXngjxAvVjksIHhCQzHbH7FU0C5qfur0 TZ3wXtbFOL/kjwvMjxuDu+qjeVtpHSfQRfbtUtu6kB0u261CZ/pdS5kYR69Nu0gUEfdN5U3Wzily7 DmFo3wXRVeVvTqqMbAHgk8ER9TGfSn53xMeF3uou7W8dZlN87/Ita/YOy4lXgc3MvjnP0ZEjStP6g uLa2npqw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ceOml-0005jF-6y; Thu, 16 Feb 2017 16:19:59 +0000 Received: from relmlor4.renesas.com ([210.160.252.174] helo=relmlie3.idc.renesas.com) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ceOm9-00053k-8z for linux-arm-kernel@lists.infradead.org; Thu, 16 Feb 2017 16:19:26 +0000 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie3.idc.renesas.com with ESMTP; 17 Feb 2017 01:19:00 +0900 Received: from relmlac1.idc.renesas.com (relmlac1.idc.renesas.com [10.200.69.21]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id 22CFA463BB; Fri, 17 Feb 2017 01:19:00 +0900 (JST) Received: by relmlac1.idc.renesas.com (Postfix, from userid 0) id 1E05280030; Fri, 17 Feb 2017 01:19:00 +0900 (JST) Received: from relmlac1.idc.renesas.com (localhost [127.0.0.1]) by relmlac1.idc.renesas.com (Postfix) with ESMTP id 183118002F; Fri, 17 Feb 2017 01:19:00 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac1.idc.renesas.com with ESMTP id BAA13244; Fri, 17 Feb 2017 01:19:00 +0900 X-IronPort-AV: E=Sophos;i="5.35,169,1483974000"; d="scan'208";a="234013162" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii1.idc.renesas.com with ESMTP; 17 Feb 2017 01:18:57 +0900 Received: from localhost.localdomain (unknown [143.103.58.208]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id DA0EB5DD; Thu, 16 Feb 2017 16:18:50 +0000 (UTC) From: Chris Brandt To: Simon Horman , Magnus Damm , Geert Uytterhoeven , Rob Herring , Mark Rutland , Russell King , Brad Mouring , Andrey Smirnov , Arnd Bergmann , Richard Cochran Subject: [PATCH v4 1/3] ARM: l2c: allow CA9 optimizations to be disabled Date: Thu, 16 Feb 2017 11:17:40 -0500 Message-Id: <20170216161742.29320-2-chris.brandt@renesas.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170216161742.29320-1-chris.brandt@renesas.com> References: <20170216161742.29320-1-chris.brandt@renesas.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170216_081921_648418_3749D2FA X-CRM114-Status: GOOD ( 11.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Brandt , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP If a PL310 is added to a system, but the sideband signals are not connected, some Cortex A9 optimizations cannot be used. In particular, enabling Full Line of Zeros in the CA9 without sidebands connected will crash the system since the CA9 will expect the L2C to perform operations, yet the L2C never gets the commands. Early BRESP also does not work without sideband signals. Signed-off-by: Chris Brandt --- v3: * changed l2x0_bresp_dis to l2x0_bresp_disable * changed l2x0_flz_dis to l2x0_flz_disable v2: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" --- Documentation/devicetree/bindings/arm/l2c2x0.txt | 3 +++ arch/arm/mm/cache-l2x0.c | 13 +++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt index 917199f..d9650c1 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -90,6 +90,9 @@ Optional properties: - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable), <1> (forcibly enable), property absent (OS specific behavior, preferably retain firmware settings) +- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310) +- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero + write (PL310) Example: diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 2290be3..808efbb 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -57,6 +57,9 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; struct l2x0_regs l2x0_saved_regs; +static bool l2x0_bresp_disable; +static bool l2x0_flz_disable; + /* * Common code for all cache controllers. */ @@ -620,7 +623,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock) u32 aux = l2x0_saved_regs.aux_ctrl; if (rev >= L310_CACHE_ID_RTL_R2P0) { - if (cortex_a9) { + if (cortex_a9 && !l2x0_bresp_disable) { aux |= L310_AUX_CTRL_EARLY_BRESP; pr_info("L2C-310 enabling early BRESP for Cortex-A9\n"); } else if (aux & L310_AUX_CTRL_EARLY_BRESP) { @@ -629,7 +632,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock) } } - if (cortex_a9) { + if (cortex_a9 && !l2x0_flz_disable) { u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL); u32 acr = get_auxcr(); @@ -1200,6 +1203,12 @@ static void __init l2c310_of_parse(const struct device_node *np, *aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE; } + if (of_property_read_bool(np, "arm,early-bresp-disable")) + l2x0_bresp_disable = true; + + if (of_property_read_bool(np, "arm,full-line-zero-disable")) + l2x0_flz_disable = true; + prefetch = l2x0_saved_regs.prefetch_ctrl; ret = of_property_read_u32(np, "arm,double-linefill", &val);