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Tue, 28 Feb 2017 06:46:52 +0000 Received: from mx2.suse.de ([195.135.220.15]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cibOr-00083V-8k for linux-arm-kernel@lists.infradead.org; Tue, 28 Feb 2017 06:36:51 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id D79E8ADCD; Tue, 28 Feb 2017 06:35:56 +0000 (UTC) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: arm@kernel.org Subject: [PATCH v3 11/25] ARM: dts: Add Actions Semi S500 and LeMaker Guitar Date: Tue, 28 Feb 2017 07:35:21 +0100 Message-Id: <20170228063535.32069-12-afaerber@suse.de> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170228063535.32069-1-afaerber@suse.de> References: <20170228063535.32069-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170227_223642_009972_2C21CC63 X-CRM114-Status: GOOD ( 13.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , support@lemaker.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Russell King , Rob Herring , mp-cs@actions-semi.com, 96boards@ucrobotics.com, =?UTF-8?q?Andreas=20F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Andreas Färber --- v2 -> v3: * Fixed uart2 reg offset * Enlarged timer reg size * Added 2 Hz timer interrupts, interrupt-names * Disabled CPUs 1-3 for now (cf. later patches) * Added Cortex-A9 SCU, global timer, TWD timer/wdt nodes * Added HOSC clock for timer v1 -> v2: * Reworded subject * Updated ARCH_OWL to ARCH_ACTIONS (Arnd) * Adopted "actions" vendor prefix * Dropped irq.h include * Added memory@0 node for Guitar SoM * Dropped bogus uart3 clock-frequency * Added device_type for CPU nodes * Fixed UART reg size * Adopted SPDX-License-Identifier (Rob) * Added remaining UART nodes * Added timer node arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/s500-guitar-bb-rev-b.dts | 26 +++++ arch/arm/boot/dts/s500-guitar.dtsi | 24 ++++ arch/arm/boot/dts/s500.dtsi | 170 +++++++++++++++++++++++++++++ 4 files changed, 222 insertions(+) create mode 100644 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts create mode 100644 arch/arm/boot/dts/s500-guitar.dtsi create mode 100644 arch/arm/boot/dts/s500.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0118084..578a20b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -638,6 +638,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-maxtor-shared-storage-2.dtb \ orion5x-netgear-wnr854t.dtb \ orion5x-rd88f5182-nas.dtb +dtb-$(CONFIG_ARCH_ACTIONS) += \ + s500-guitar-bb-rev-b.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb dtb-$(CONFIG_ARCH_OXNAS) += \ diff --git a/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts new file mode 100644 index 0000000..834b71d --- /dev/null +++ b/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2016-2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "s500-guitar.dtsi" + +/ { + compatible = "lemaker,guitar-bb-rev-b", "lemaker,guitar", "actions,s500"; + model = "LeMaker Guitar Base Board rev. B"; + + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/s500-guitar.dtsi b/arch/arm/boot/dts/s500-guitar.dtsi new file mode 100644 index 0000000..31c5def --- /dev/null +++ b/arch/arm/boot/dts/s500-guitar.dtsi @@ -0,0 +1,24 @@ +/* + * LeMaker Guitar SoM + * + * Copyright (c) 2016-2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#include "s500.dtsi" + +/ { + compatible = "lemaker,guitar", "actions,s500"; + + /delete-node/ memory; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; +}; + +&timer { + clocks = <&hosc>; +}; diff --git a/arch/arm/boot/dts/s500.dtsi b/arch/arm/boot/dts/s500.dtsi new file mode 100644 index 0000000..1973181 --- /dev/null +++ b/arch/arm/boot/dts/s500.dtsi @@ -0,0 +1,170 @@ +/* + * Actions Semi S500 SoC + * + * Copyright (c) 2016-2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#include "skeleton.dtsi" + +#include + +/ { + compatible = "actions,s500"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x3>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + hosc: hosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + scu: scu@b0020000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xb0020000 0x100>; + }; + + global_timer: timer@b0020200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xb0020200 0x100>; + interrupts = ; + status = "disabled"; + }; + + twd_timer: timer@b0020600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xb0020600 0x20>; + interrupts = ; + status = "disabled"; + }; + + twd_wdt: wdt@b0020620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xb0020620 0xe0>; + interrupts = ; + status = "disabled"; + }; + + gic: interrupt-controller@b0021000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xb0021000 0x1000>, + <0xb0020100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + l2: cache-controller@b0022000 { + compatible = "arm,pl310-cache"; + reg = <0xb0022000 0x1000>; + cache-unified; + cache-level = <2>; + interrupts = ; + arm,tag-latency = <3 3 2>; + arm,data-latency = <5 3 3>; + }; + + uart0: serial@b0120000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0120000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + uart1: serial@b0122000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0122000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + uart2: serial@b0124000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0124000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + uart3: serial@b0126000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0126000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + uart4: serial@b0128000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0128000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + uart5: serial@b012a000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb012a000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + uart6: serial@b012c000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb012c000 0x2000>; + interrupts = ; + status = "disabled"; + }; + + timer: timer@b0168000 { + compatible = "actions,s500-timer", "actions,owl-timer"; + reg = <0xb0168000 0x8000>; + interrupts = , + , + , + ; + interrupt-names = "2Hz0", "2Hz1", "Timer0", "Timer1"; + }; + }; +};