From patchwork Mon Mar 27 09:49:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 9646357 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6FF4960328 for ; Mon, 27 Mar 2017 10:21:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6EE6A28364 for ; Mon, 27 Mar 2017 10:21:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 62EC428384; Mon, 27 Mar 2017 10:21:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E0D0428364 for ; Mon, 27 Mar 2017 10:21:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=xsyijjJJ8UUXUCPObTDIqiOdcySsuRmannf4EieckJo=; b=LKSqGeXYnLxqAUCTmsMBM9louS W3GoEf/1KJh6LCXHR0r0iQYoTu+EO6DBqsSB06liKHfgQeuTPjI7sDcRQqTPfPyVbC7S5Ld1rMp2f ZWLX87L7StEfsKK9065jebx6skaKEvteWdXYBMhmsT1VoZXzcq72Wd278mdaISTUQgYrz04U58wXj 2YUBWA1hfPktNWtRdFivoMHQ17IjTovxaJ5O6rdX3WzuQpZ9yGNEZyL4+Gi/1lfU26GZkdl0Rzmxq qTGTEu6i/meT+g4kEYtriJ2H2ZArpcHDuj/CXGgGKdd2iuHg0BYD9OMjcsqyLuH3CkF59GZ7ffkFV avxXXXLg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1csRlp-0007MD-FL; Mon, 27 Mar 2017 10:21:05 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1csRIQ-0004qY-0x for linux-arm-kernel@bombadil.infradead.org; Mon, 27 Mar 2017 09:50:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=h2CpF+JuRG7j+j+bF/d1GtFYt9sB+uFYAaXeqUAnIGU=; b=qaVnKAUsgClYDxvn7/UIXKns2 DJ8xk7tvfnOx542eNla0gvP66VcXayzZUlWCgd2qxm4HPFJfjEeW+HNQcFAsEM2TfzMitxODlXV7i D12f2I6ITrp6BbtvngVXhRVlaZ3Ft2xo1zvhIt8H1en+WwNTRVzC/KSuGJyZoIvcKSYhULnPNxkql UFo/riqNCcMD7v5cuy8Mb0j6RrMn3zdExISkuECpZam0+v8863SdIavs+yvJLsM6UpQN65qsiRhy8 tdZY/i0NhK52lPjCFNH0cNt5dyZ461CBMznsTqRHneijePny0ZmVpch3hikaY9YI64IaY4RaUIIs8 w74A5ojqA==; Received: from foss.arm.com ([217.140.101.70]) by casper.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1csRIM-0004Ax-1k for linux-arm-kernel@lists.infradead.org; Mon, 27 Mar 2017 09:50:40 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BAFDD1478; Mon, 27 Mar 2017 02:50:16 -0700 (PDT) Received: from red-moon.cambridge.arm.com (red-moon.cambridge.arm.com [10.1.206.55]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9CB7E3F23B; Mon, 27 Mar 2017 02:50:11 -0700 (PDT) From: Lorenzo Pieralisi To: linux-pci@vger.kernel.org Subject: [PATCH v2 06/22] ARM: implement ioremap_nopost() interface Date: Mon, 27 Mar 2017 10:49:34 +0100 Message-Id: <20170327094954.7162-7-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20170327094954.7162-1-lorenzo.pieralisi@arm.com> References: <20170327094954.7162-1-lorenzo.pieralisi@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170327_105038_385551_82F70875 X-CRM114-Status: GOOD ( 14.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Wenrui Li , Gabriele Paoloni , Catalin Marinas , Shawn Lin , Will Deacon , Michal Simek , Thierry Reding , Tanmay Inamdar , Lorenzo Pieralisi , Pratyush Anand , Russell King , Jon Mason , Murali Karicheri , Arnd Bergmann , Bharat Kumar Gogada , Ray Jui , John Garry , Joao Pinto , Bjorn Helgaas , Mingkai Hu , linux-arm-kernel@lists.infradead.org, "Luis R. Rodriguez" , Thomas Petazzoni , Jingoo Han , linux-kernel@vger.kernel.org, Stanimir Varbanov , Minghuan Lian , Zhou Wang , Roy Zang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The PCI bus specifications (rev 3.0, 3.2.5 "Transaction Ordering and Posting") define rules for PCI configuration space transactions ordering and posting, that state that configuration writes have to be non-posted transactions. Current ioremap interface on ARM provides mapping functions that provide "bufferable" writes transactions (ie ioremap uses MT_DEVICE memory type) aka posted writes, so PCI host controller drivers have no arch interface to remap PCI configuration space with memory attributes that comply with the PCI specifications for configuration space. Implement an ARM specific ioremap_nopost() interface that allows to map PCI config memory regions with MT_UNCACHED memory type (ie strongly ordered - non-posted writes), providing a remap function that complies with PCI specifications for config space transactions. Signed-off-by: Lorenzo Pieralisi Cc: Arnd Bergmann Cc: Russell King --- arch/arm/include/asm/io.h | 10 ++++++++++ arch/arm/mm/ioremap.c | 7 +++++++ arch/arm/mm/nommu.c | 9 +++++++++ 3 files changed, 26 insertions(+) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 42871fb..49913d1 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -352,6 +352,7 @@ static inline void memcpy_toio(volatile void __iomem *to, const void *from, * mapping has specific properties. * * Function Memory type Cacheability Cache hint + * ioremap_nopost() SO n/a n/a * ioremap() Device n/a n/a * ioremap_nocache() Device n/a n/a * ioremap_cache() Normal Writeback Read allocate @@ -372,6 +373,12 @@ static inline void memcpy_toio(volatile void __iomem *to, const void *from, * compiler may generate unaligned accesses - eg, via inlining its own * memcpy. * + * ioremap_nopost() maps memory as strongly ordered, to be used for + * specific mappings (eg PCI config space) that require non-posted + * write transactions. Strongly ordered transactions are ordered wrt + * device mappings, which means that ioremap_nopost() is the same + * as ioremap() except for non-posted writes behaviour. + * * All normal memory mappings have the following properties: * - reads can be repeated with no side effects * - repeated reads return the last value written @@ -407,6 +414,9 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size); #define ioremap_wc ioremap_wc #define ioremap_wt ioremap_wc +void __iomem *ioremap_nopost(resource_size_t res_cookie, size_t size); +#define ioremap_nopost ioremap_nopost + void iounmap(volatile void __iomem *iomem_cookie); #define iounmap iounmap diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index ff0eed2..4ffaf16 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -463,6 +463,13 @@ void iounmap(volatile void __iomem *cookie) } EXPORT_SYMBOL(iounmap); +void __iomem *ioremap_nopost(resource_size_t res_cookie, size_t size) +{ + return arch_ioremap_caller(res_cookie, size, MT_UNCACHED, + __builtin_return_address(0)); +} +EXPORT_SYMBOL_GPL(ioremap_nopost); + #ifdef CONFIG_PCI static int pci_ioremap_mem_type = MT_DEVICE; diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 3b5c7aa..dfd736a 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -21,6 +21,8 @@ #include #include +#include + #include "mm.h" unsigned long vectors_base; @@ -433,6 +435,13 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size) } EXPORT_SYMBOL(ioremap_wc); +void __iomem *ioremap_nopost(resource_size_t res_cookie, size_t size) +{ + return __arm_ioremap_caller(res_cookie, size, MT_UNCACHED, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(ioremap_nopost); + void *arch_memremap_wb(phys_addr_t phys_addr, size_t size) { return (void *)phys_addr;