From patchwork Thu Mar 30 08:10:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 9653195 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8B90D602C8 for ; Thu, 30 Mar 2017 08:21:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 790CA26BE9 for ; Thu, 30 Mar 2017 08:21:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6C27F28520; Thu, 30 Mar 2017 08:21:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DB53526BE9 for ; Thu, 30 Mar 2017 08:21:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=KYxEXUsvY3QQB5AdaXM6xau0t+uTjfNjDUx4t6P61ZQ=; b=RGEFrn2zb1kTyj72ZE8A9RWHH3 aoAKhAnblhCxbN6dmw2nVUyoKaakSeLDLGD57VqKLQGnbKzd312BcMFnev+eR5YRFQQ911eSf9EbM yRNsNijVqKQbGqaQ9RmSsRPcJuSShRIh5RW8+wN/43F4K2/ce8Ff0xqluUiluAK/ol7qZgYgxYMOE 4CPZ3YKZEXnUe5xZvb7La/KOlcsCJB6AGeI3lPjVDIM8yAJBLbasHcRQPSdCq3wJkFSzmY+LRV+WO lNZPe6DPktymcjkfCBmm0VND7WbDeA+QqYtjUw8KrN5uvOKxzMfO1G4gtDT8NwuQC/Dqyrcls4kh9 RDW146vQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ctVKG-0005qM-6r; Thu, 30 Mar 2017 08:21:00 +0000 Received: from burlywood.ash.relay.mailchannels.net ([23.83.222.26]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1ctVAs-0001B3-UL for linux-arm-kernel@lists.infradead.org; Thu, 30 Mar 2017 08:11:21 +0000 X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id 6D16C7C2223; Thu, 30 Mar 2017 08:10:51 +0000 (UTC) Received: from hermes.aosc.io (unknown [100.96.137.101]) by relay.mailchannels.net (Postfix) with ESMTPA id E1DD07C2074; Thu, 30 Mar 2017 08:10:50 +0000 (UTC) X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from hermes.aosc.io (hermes.aosc.io [172.20.72.20]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384) by 0.0.0.0:2500 (trex/5.7.37); Thu, 30 Mar 2017 08:10:51 +0000 X-MC-Relay: Neutral X-MailChannels-SenderId: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io X-MailChannels-Auth-Id: lmn-TZDUIOWCRQMW X-Glossy-Harmony: 1e71e6144a5c5cc9_1490861451199_2828609810 X-MC-Loop-Signature: 1490861451199:2159681898 X-MC-Ingress-Time: 1490861451198 Received: from localhost.localdomain (unknown [120.236.174.154]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 82DC97E72C; Thu, 30 Mar 2017 08:10:43 +0000 (UTC) From: Icenowy Zheng To: Srinivas Kandagatla , Maxime Ripard , Chen-Yu Tsai Subject: [PATCH v6 2/3] nvmem: sunxi-sid: add support for H3's SID controller Date: Thu, 30 Mar 2017 16:10:18 +0800 Message-Id: <20170330081019.59979-2-icenowy@aosc.io> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170330081019.59979-1-icenowy@aosc.io> References: <20170330081019.59979-1-icenowy@aosc.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170330_011119_672877_728E8C6B X-CRM114-Status: GOOD ( 18.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Icenowy Zheng The H3 SoC have a bigger SID controller, which has its direct read address at 0x200 position in the SID block, not 0x0. Also, H3 SID controller has some silicon bug that makes the direct read value wrong at cold boot, add code to workaround the bug. (This bug has already been fixed on A64 and later SoCs) Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard --- Changes in v6: - Add Maxime's ACK. Changes in v5: - Removed some bits in binding documentation. - Removed some default values in cfg struct. Changes in v4: - Use readl_poll_timeout. - Do register offset in sunxi_sid_read. - Merge SUN8I_SID_OP_LOCK and SUN8I_SID_LOCK_SHIFT into one macro. - Drop the result of register-based read operation. Srinivas Kandagatla said that this patch have been queued when it's v5, however it haven't hit linux-next now. .../bindings/nvmem/allwinner,sunxi-sid.txt | 6 ++- drivers/nvmem/sunxi_sid.c | 62 ++++++++++++++++++++++ 2 files changed, 67 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt index d543ed3f5363..ef06d061913c 100644 --- a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt @@ -1,7 +1,11 @@ Allwinner sunxi-sid Required properties: -- compatible: "allwinner,sun4i-a10-sid" or "allwinner,sun7i-a20-sid" +- compatible: Should be one of the following: + "allwinner,sun4i-a10-sid" + "allwinner,sun7i-a20-sid" + "allwinner,sun8i-h3-sid" + - reg: Should contain registers location and length = Data cells = diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c index 69524b67007f..0d6648be93b8 100644 --- a/drivers/nvmem/sunxi_sid.c +++ b/drivers/nvmem/sunxi_sid.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -25,6 +26,15 @@ #include #include +/* Registers and special values for doing register-based SID readout on H3 */ +#define SUN8I_SID_PRCTL 0x40 +#define SUN8I_SID_RDKEY 0x60 + +#define SUN8I_SID_OFFSET_MASK 0x1FF +#define SUN8I_SID_OFFSET_SHIFT 16 +#define SUN8I_SID_OP_LOCK (0xAC << 8) +#define SUN8I_SID_READ BIT(1) + static struct nvmem_config econfig = { .name = "sunxi-sid", .read_only = true, @@ -34,11 +44,14 @@ static struct nvmem_config econfig = { }; struct sunxi_sid_cfg { + u32 value_offset; u32 size; + bool need_register_readout; }; struct sunxi_sid { void __iomem *base; + u32 value_offset; }; /* We read the entire key, due to a 32 bit read alignment requirement. Since we @@ -63,12 +76,36 @@ static int sunxi_sid_read(void *context, unsigned int offset, struct sunxi_sid *sid = context; u8 *buf = val; + /* Offset the read operation to the real position of SID */ + offset += sid->value_offset; + while (bytes--) *buf++ = sunxi_sid_read_byte(sid, offset++); return 0; } +static int sun8i_sid_register_readout(const struct sunxi_sid *sid, + const unsigned int word) +{ + u32 reg_val; + int ret; + + /* Set word, lock access, and set read command */ + reg_val = (word & SUN8I_SID_OFFSET_MASK) + << SUN8I_SID_OFFSET_SHIFT; + reg_val |= SUN8I_SID_OP_LOCK | SUN8I_SID_READ; + writel(reg_val, sid->base + SUN8I_SID_PRCTL); + + ret = readl_poll_timeout(sid->base + SUN8I_SID_PRCTL, reg_val, + !(reg_val & SUN8I_SID_READ), 100, 250000); + if (ret) + return ret; + + writel(0, sid->base + SUN8I_SID_PRCTL); + return 0; +} + static int sunxi_sid_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -86,6 +123,7 @@ static int sunxi_sid_probe(struct platform_device *pdev) cfg = of_device_get_match_data(dev); if (!cfg) return -EINVAL; + sid->value_offset = cfg->value_offset; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); sid->base = devm_ioremap_resource(dev, res); @@ -94,6 +132,23 @@ static int sunxi_sid_probe(struct platform_device *pdev) size = cfg->size; + if (cfg->need_register_readout) { + /* + * H3's SID controller have a bug that the value at 0x200 + * offset is not the correct value when the hardware is reseted. + * However, after doing a register-based read operation, the + * value become right. + * Do a full read operation here, but ignore its value + * (as it's more fast to read by direct MMIO value than + * with registers) + */ + for (i = 0; i < (size >> 2); i++) { + ret = sun8i_sid_register_readout(sid, i); + if (ret) + return ret; + } + } + econfig.size = size; econfig.dev = dev; econfig.reg_read = sunxi_sid_read; @@ -138,9 +193,16 @@ static const struct sunxi_sid_cfg sun7i_a20_cfg = { .size = 0x200, }; +static const struct sunxi_sid_cfg sun8i_h3_cfg = { + .value_offset = 0x200, + .size = 0x100, + .need_register_readout = true, +}; + static const struct of_device_id sunxi_sid_of_match[] = { { .compatible = "allwinner,sun4i-a10-sid", .data = &sun4i_a10_cfg }, { .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg }, + { .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg }, {/* sentinel */}, }; MODULE_DEVICE_TABLE(of, sunxi_sid_of_match);