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[93.227.134.66]) by smtp.googlemail.com with ESMTPSA id b42sm10701660wra.36.2017.04.01.06.59.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 01 Apr 2017 06:59:36 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, linux-gpio@vger.kernel.org, khilman@baylibre.com, carlo@caione.org, linus.walleij@linaro.org Subject: [PATCH v2 2/2] pinctrl: meson: meson8b: rename the NAND DQS pin definitions Date: Sat, 1 Apr 2017 15:59:22 +0200 Message-Id: <20170401135922.1288-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.12.1 In-Reply-To: <20170401135922.1288-1-martin.blumenstingl@googlemail.com> References: <20170325184350.7677-1-martin.blumenstingl@googlemail.com> <20170401135922.1288-1-martin.blumenstingl@googlemail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170401_065959_055497_60C9A42D X-CRM114-Status: GOOD ( 10.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The NAND DQS pins are currently named nand_dqs_0 and nand_dqs_1. However, they both seem to have the same function, just exposed on different pins (unlike the ethernet TX pins for example, where there's eth_txd0..3 - all of these can be active at the same time as they are different data lines). Rename the NAND DQS pins to nand_dqs_15 and nand_dqs_18 to reflect that it's the same functionality just exposed on different pins (BOOT_15 and BOOT_18). Signed-off-by: Martin Blumenstingl Acked-by: Kevin Hilman --- drivers/pinctrl/meson/pinctrl-meson8b.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c index f87ef5a0ee6c..bf747eb1f3f4 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8b.c +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c @@ -267,8 +267,8 @@ static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) }; static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) }; static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) }; static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) }; -static const unsigned int nand_dqs_0_pins[] = { PIN(BOOT_15, 0) }; -static const unsigned int nand_dqs_1_pins[] = { PIN(BOOT_18, 0) }; +static const unsigned int nand_dqs_15_pins[] = { PIN(BOOT_15, 0) }; +static const unsigned int nand_dqs_18_pins[] = { PIN(BOOT_18, 0) }; static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)}; static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0), @@ -527,8 +527,8 @@ static struct meson_pmx_group meson8b_cbus_groups[] = { GROUP(nand_cle, 2, 20), GROUP(nand_wen_clk, 2, 19), GROUP(nand_ren_clk, 2, 18), - GROUP(nand_dqs_0, 2, 27), - GROUP(nand_dqs_1, 2, 28), + GROUP(nand_dqs_15, 2, 27), + GROUP(nand_dqs_18, 2, 28), GROUP(sdxc_d0_c, 4, 30), GROUP(sdxc_d13_c, 4, 29), GROUP(sdxc_d47_c, 4, 28), @@ -739,8 +739,8 @@ static const char * const sdxc_c_groups[] = { static const char * const nand_groups[] = { "nand_io", "nand_io_ce0", "nand_io_ce1", "nand_io_rb0", "nand_ale", "nand_cle", - "nand_wen_clk", "nand_ren_clk", "nand_dqs_0", - "nand_dqs_1" + "nand_wen_clk", "nand_ren_clk", "nand_dqs_15", + "nand_dqs_18" }; static const char * const nor_groups[] = {