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[90.116.208.57]) by smtp.googlemail.com with ESMTPSA id z84sm4727104wmh.27.2017.04.12.04.16.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 12 Apr 2017 04:16:20 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com Subject: [PATCH v4 13/18] arm64: allwinner: sun50i-a64: add dwmac-sun8i Ethernet driver Date: Wed, 12 Apr 2017 13:13:55 +0200 Message-Id: <20170412111400.2296-14-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170412111400.2296-1-clabbe.montjoie@gmail.com> References: <20170412111400.2296-1-clabbe.montjoie@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170412_041642_394007_006F174B X-CRM114-Status: UNSURE ( 9.24 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The dwmac-sun8i is an Ethernet MAC that supports 10/100/1000 Mbit connections. It is very similar to the device found in the Allwinner H3, but lacks the internal 100 Mbit PHY and its associated control bits. This adds the necessary bits to the Allwinner A64 SoC .dtsi, but keeps it disabled at this level. Signed-off-by: Corentin Labbe --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 0b0f4ab..2569827 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -287,6 +287,23 @@ bias-pull-up; }; + rmii_pins: rmii_pins { + pins = "PD10", "PD11", "PD13", "PD14", + "PD17", "PD18", "PD19", "PD20", + "PD22", "PD23"; + function = "emac"; + drive-strength = <40>; + }; + + rgmii_pins: rgmii_pins { + pins = "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD15", + "PD16", "PD17", "PD18", "PD19", + "PD20", "PD21", "PD22", "PD23"; + function = "emac"; + drive-strength = <40>; + }; + uart0_pins_a: uart0@0 { pins = "PB8", "PB9"; function = "uart0"; @@ -391,6 +408,26 @@ #size-cells = <0>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun50i-a64-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x100>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>,