Message ID | 20170416120849.54542-11-icenowy@aosc.io (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Sun, 16 Apr 2017 12:11:51 +0000 (UTC) From: Icenowy Zheng <icenowy@aosc.io> To: Rob Herring <robh+dt@kernel.org>, Maxime Ripard <maxime.ripard@free-electrons.com>, Chen-Yu Tsai <wens@csie.org>, David Airlie <airlied@linux.ie>, Jernej Skrabec <jernej.skrabec@siol.net> Subject: [PATCH v4 10/11] ARM: dts: sun8i: add pinmux for LCD pins of V3s SoC Date: Sun, 16 Apr 2017 20:08:48 +0800 Message-Id: <20170416120849.54542-11-icenowy@aosc.io> In-Reply-To: <20170416120849.54542-1-icenowy@aosc.io> References: <20170416120849.54542-1-icenowy@aosc.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170416_081223_304803_C6DAD7AC X-CRM114-Status: UNSURE ( 6.89 ) X-CRM114-Notice: Please train this message. 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diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index ae23746731a8..ac783a8a4fd3 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -297,6 +297,15 @@ function = "i2c0"; }; + lcd_rgb666_pins: lcd_rgb666@0 { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9", + "PE10", "PE11", "PE12", "PE13", "PE14", + "PE15", "PE16", "PE17", "PE18", "PE19", + "PE23", "PE24"; + function = "lcd"; + }; + uart0_pins_a: uart0@0 { pins = "PB8", "PB9"; function = "uart0";
Allwinner V3s SoC features a set of pins that have functionality of RGB LCD, the pins are at different pin ban than other SoCs. Add pinctrl node for them. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)