From patchwork Wed Apr 26 16:13:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 9701695 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 96F7E6032C for ; Wed, 26 Apr 2017 16:13:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 87265285F8 for ; Wed, 26 Apr 2017 16:13:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 79EBC28602; Wed, 26 Apr 2017 16:13:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EEC43285F8 for ; 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Wed, 26 Apr 2017 16:13:15 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1d3PZ2-0008SM-OV for linux-arm-kernel@lists.infradead.org; Wed, 26 Apr 2017 16:13:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84BA715A1; Wed, 26 Apr 2017 09:12:52 -0700 (PDT) Received: from red-moon (red-moon.cambridge.arm.com [10.1.206.55]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 746E73F3E1; Wed, 26 Apr 2017 09:12:48 -0700 (PDT) Date: Wed, 26 Apr 2017 17:13:35 +0100 From: Lorenzo Pieralisi To: Andrew Lunn Subject: Re: [RFC/RFT PATCH 07/18] ARM: PCI: orion5x: Convert PCI scan API to pci_scan_root_bus_bridge() Message-ID: <20170426161335.GA12240@red-moon> References: <20170426111809.19922-1-lorenzo.pieralisi@arm.com> <20170426111809.19922-8-lorenzo.pieralisi@arm.com> <20170426151257.GA4489@lunn.ch> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20170426151257.GA4489@lunn.ch> User-Agent: Mutt/1.5.21 (2010-09-15) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170426_091312_807130_6C17F0FF X-CRM114-Status: GOOD ( 18.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Pratyush Anand , Gabriele Paoloni , linux-pci@vger.kernel.org, Shawn Lin , Will Deacon , Michal Simek , Thierry Reding , Tanmay Inamdar , Matthew Minter , Rob Herring , Joao Pinto , Wenrui Li , Russell King , Murali Karicheri , Jason Cooper , Arnd Bergmann , Bharat Kumar Gogada , Simon Horman , Bjorn Helgaas , Mingkai Hu , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Jingoo Han , Stanimir Varbanov , Minghuan Lian , Zhou Wang , Roy Zang Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On Wed, Apr 26, 2017 at 05:12:57PM +0200, Andrew Lunn wrote: > On Wed, Apr 26, 2017 at 12:17:58PM +0100, Lorenzo Pieralisi wrote: > > The introduction of pci_scan_root_bus_bridge() provides a PCI core > > API to scan a PCI root bus backed by an already initialized > > struct pci_host_bridge object, which simplifies the bus scan > > interface and makes the PCI scan root bus interface easier to > > generalize as members are added to the struct pci_host_bridge(). > > > > Convert ARM orion5x platform code to pci_scan_root_bus_bridge() to > > improve the PCI root bus scanning interface. > > Hi Lorenzo > > Maybe there is something not right here. > > With plain 4.11-rc7 i get: > > root@orion5x:~# lspci -v > 0000:00:00.0 Memory controller: Marvell Technology Group Ltd. 88f5182 [Orion-NAS] ARM SoC (rev 02) > Subsystem: Marvell Technology Group Ltd. Device 11ab > Flags: bus master, fast devsel, latency 0, IRQ 12 > Memory at (64-bit, prefetchable) > Capabilities: [40] Power Management version 2 > Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ > Capabilities: [60] Express Root Port (Slot-), MSI 00 > > 0001:01:00.0 Memory controller: Marvell Technology Group Ltd. 88f5182 [Orion-NAS] ARM SoC (rev 02) > Flags: bus master, fast Back2Back, 66MHz, medium devsel, latency 0 > BIST result: 00 > Memory at (64-bit, prefetchable) > Memory at (64-bit, prefetchable) > Memory at (64-bit, non-prefetchable) > Expansion ROM at [disabled] > Capabilities: [40] Power Management version 2 > Capabilities: [48] Vital Product Data > Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ > Capabilities: [60] PCI-X non-bridge device > Capabilities: [68] CompactPCI hot-swap > > However, with your patches applied i get: > > 0000:00:00.0 Memory controller: Marvell Technology Group Ltd. 88f5182 [Orion-NAS] ARM SoC (rev 02) > Subsystem: Marvell Technology Group Ltd. Device 11ab > Flags: bus master, fast devsel, latency 0 > Memory at (64-bit, prefetchable) > Capabilities: [40] Power Management version 2 > Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ > Capabilities: [60] Express Root Port (Slot-), MSI 00 > > 0001:01:00.0 Memory controller: Marvell Technology Group Ltd. 88f5182 [Orion-NAS] ARM SoC (rev 02) > Flags: bus master, fast Back2Back, 66MHz, medium devsel, latency 0 > BIST result: 00 > Memory at (64-bit, prefetchable) > Memory at (64-bit, prefetchable) > Memory at (64-bit, non-prefetchable) > Expansion ROM at [disabled] > Capabilities: [40] Power Management version 2 > Capabilities: [48] Vital Product Data > Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ > Capabilities: [60] PCI-X non-bridge device > Capabilities: [68] CompactPCI hot-swap > > Note that IRQ 12 has disappeared from Flags: on 0000:00:00.0. Thank you for testing it, that's exactly what we need. To check if the plumbing is working (ie to check I have not messed up the bus scan API rework), mind testing the patch below please and report back (it applies on top of this series) ? Thanks ! Lorenzo -- >8 -- diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 4632fa4..afa7271 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -400,8 +400,6 @@ static int pci_device_probe(struct device *dev) struct pci_dev *pci_dev = to_pci_dev(dev); struct pci_driver *drv = to_pci_driver(dev->driver); - pci_assign_irq(pci_dev); - error = pcibios_alloc_irq(pci_dev); if (error < 0) return error; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index de259f3..dc9a1b6 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1967,6 +1967,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) ret = pcibios_add_device(dev); WARN_ON(ret < 0); + pci_assign_irq(dev); + /* Setup MSI irq domain */ pci_set_msi_domain(dev);