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Thu, 4 May 2017 11:51:05 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Rob Herring , Chen-Yu Tsai Subject: [PATCH v6 12/13] ARM: dts: sun8i: add pinmux for LCD pins of V3s SoC Date: Thu, 4 May 2017 19:48:57 +0800 Message-Id: <20170504114858.9008-13-icenowy@aosc.io> In-Reply-To: <20170504114858.9008-1-icenowy@aosc.io> References: <20170504114858.9008-1-icenowy@aosc.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170504_075140_041196_63F4ACBC X-CRM114-Status: UNSURE ( 7.72 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Allwinner V3s SoC features a set of pins that have functionality of RGB LCD, the pins are at different pin ban than other SoCs. Add pinctrl node for them. Signed-off-by: Icenowy Zheng Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 0a895179d8ae..a37d68b227bc 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -297,6 +297,15 @@ function = "i2c0"; }; + lcd_rgb666_pins: lcd_rgb666@0 { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9", + "PE10", "PE11", "PE12", "PE13", "PE14", + "PE15", "PE16", "PE17", "PE18", "PE19", + "PE23", "PE24"; + function = "lcd"; + }; + uart0_pins_a: uart0@0 { pins = "PB8", "PB9"; function = "uart0";