From patchwork Tue May 30 21:51:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Belloni X-Patchwork-Id: 9755507 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9E477602F0 for ; Tue, 30 May 2017 22:04:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 904AA26E97 for ; Tue, 30 May 2017 22:04:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 84C04283C9; Tue, 30 May 2017 22:04:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DBAB026E97 for ; Tue, 30 May 2017 22:04:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=qF7CZay19sVhr8eHEGatgos4bChr0Vbd3RUd4CW4dAk=; b=Ur3ZffaeZU769VUHKPN/c05kbk M48VV1BzxuAghufN9Xb1X6Qa8guDDyD35phI950BgPfjRTe0OFG3efyxXGsknM093rk3qh6GsgCzM 0ip2kk0x7x1mVXQFpTpMVntHFGdo+GdzgAQuNfDRV11NefgxxLU6co9lQ4vNqRHe4x6Tg9TXh0vLP ikl48H7Ki87PU9SiJXeZHFFxfz7nbEi5wOjCeNyqcocoo9RteVdu/wTwS+WS0smrDbLIP6UROQ7BR 3smnFV52TcVRnohAc9bjnvJriNg1zejjnOv1MiNIarFT6A1Kx+1jtljTrF4f4FY8TsCxg6oFYLW8M pEAEJdlg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dFpFj-0002Pc-9u; Tue, 30 May 2017 22:04:35 +0000 Received: from mail.free-electrons.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dFp4N-0005GQ-C1 for linux-arm-kernel@lists.infradead.org; Tue, 30 May 2017 21:52:59 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id 37BBB20F8A; Tue, 30 May 2017 23:52:39 +0200 (CEST) Received: from localhost (unknown [88.191.26.124]) by mail.free-electrons.com (Postfix) with ESMTPSA id D841D2055F; Tue, 30 May 2017 23:52:28 +0200 (CEST) From: Alexandre Belloni To: Nicolas Ferre Subject: [PATCH 48/58] clocksource/drivers: timer-atmel-tcbclksrc: add clockevent device on separate channel Date: Tue, 30 May 2017 23:51:29 +0200 Message-Id: <20170530215139.9983-49-alexandre.belloni@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170530215139.9983-1-alexandre.belloni@free-electrons.com> References: <20170530215139.9983-1-alexandre.belloni@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170530_145252_083332_D69842B0 X-CRM114-Status: GOOD ( 17.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Boris Brezillon , Daniel Lezcano , linux-kernel@vger.kernel.org, Alexandre Belloni , Thomas Gleixner , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add an other clockevent device that uses a separate TCB channel when available. Cc: Daniel Lezcano Cc: Thomas Gleixner Signed-off-by: Alexandre Belloni --- drivers/clocksource/timer-atmel-tcbclksrc.c | 177 +++++++++++++++++++++++++++- 1 file changed, 173 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-atmel-tcbclksrc.c b/drivers/clocksource/timer-atmel-tcbclksrc.c index 462b04e9fed8..e117c11b4d1c 100644 --- a/drivers/clocksource/timer-atmel-tcbclksrc.c +++ b/drivers/clocksource/timer-atmel-tcbclksrc.c @@ -32,6 +32,167 @@ static struct atmel_tcb_clksrc { }, }; +static struct tc_clkevt_device { + char name[20]; + struct clock_event_device clkevt; + struct regmap *regmap; + struct clk *slow_clk; + struct clk *clk; + int channel; + int irq; + bool registered; +} tce = { + .clkevt = { + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + /* + * Should be lower than at91rm9200's system timer + * but higher than tc.clkevt.rating + */ + .rating = 140, + }, +}; + +static int tc_clkevt2_shutdown(struct clock_event_device *d) +{ + regmap_write(tce.regmap, ATMEL_TC_IDR(tce.channel), 0xff); + regmap_write(tce.regmap, ATMEL_TC_CCR(tce.channel), + ATMEL_TC_CCR_CLKDIS); + if (!clockevent_state_detached(d)) + clk_disable(tce.clk); + + return 0; +} + +/* For now, we always use the 32K clock ... this optimizes for NO_HZ, + * because using one of the divided clocks would usually mean the + * tick rate can never be less than several dozen Hz (vs 0.5 Hz). + * + * A divided clock could be good for high resolution timers, since + * 30.5 usec resolution can seem "low". + */ +static int tc_clkevt2_set_oneshot(struct clock_event_device *d) +{ + if (clockevent_state_oneshot(d) || clockevent_state_periodic(d)) + tc_clkevt2_shutdown(d); + + clk_enable(tce.clk); + + /* slow clock, count up to RC, then irq and stop */ + regmap_write(tce.regmap, ATMEL_TC_CMR(tce.channel), + ATMEL_TC_CMR_TCLK(4) | ATMEL_TC_CMR_CPCSTOP | + ATMEL_TC_CMR_WAVE | ATMEL_TC_CMR_WAVESEL_UPRC); + regmap_write(tce.regmap, ATMEL_TC_IER(tce.channel), + ATMEL_TC_CPCS); + + return 0; +} + +static int tc_clkevt2_set_periodic(struct clock_event_device *d) +{ + if (clockevent_state_oneshot(d) || clockevent_state_periodic(d)) + tc_clkevt2_shutdown(d); + + /* By not making the gentime core emulate periodic mode on top + * of oneshot, we get lower overhead and improved accuracy. + */ + clk_enable(tce.clk); + + /* slow clock, count up to RC, then irq and restart */ + regmap_write(tce.regmap, ATMEL_TC_CMR(tce.channel), + ATMEL_TC_CMR_TCLK(4) | ATMEL_TC_CMR_WAVE | + ATMEL_TC_CMR_WAVESEL_UPRC); + regmap_write(tce.regmap, ATMEL_TC_RC(tce.channel), + (32768 + HZ / 2) / HZ); + + /* Enable clock and interrupts on RC compare */ + regmap_write(tce.regmap, ATMEL_TC_IER(tce.channel), ATMEL_TC_CPCS); + regmap_write(tce.regmap, ATMEL_TC_CCR(tce.channel), + ATMEL_TC_CCR_CLKEN | ATMEL_TC_CCR_SWTRG); + + return 0; +} + +static int tc_clkevt2_next_event(unsigned long delta, struct clock_event_device *d) +{ + regmap_write(tce.regmap, ATMEL_TC_RC(tce.channel), delta); + regmap_write(tce.regmap, ATMEL_TC_CCR(tce.channel), + ATMEL_TC_CCR_CLKEN | ATMEL_TC_CCR_SWTRG); + + return 0; +} + +static irqreturn_t tc_clkevt2_irq(int irq, void *handle) +{ + unsigned int sr; + + regmap_read(tce.regmap, ATMEL_TC_SR(tce.channel), &sr); + if (sr & ATMEL_TC_CPCS) { + tce.clkevt.event_handler(&tce.clkevt); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static int __init tc_clkevt_register(struct device_node *node, + struct regmap *regmap, int channel, + int irq, int bits) +{ + int ret; + + tce.regmap = regmap; + tce.channel = channel; + tce.irq = irq; + + tce.slow_clk = of_clk_get_by_name(node->parent, "slow_clk"); + if (IS_ERR(tce.slow_clk)) + return PTR_ERR(tce.slow_clk); + + ret = clk_prepare_enable(tce.slow_clk); + if (ret) + return ret; + + tce.clk = tcb_clk_get(node, tce.channel); + if (IS_ERR(tce.clk)) { + ret = PTR_ERR(tce.clk); + goto err_slow; + } + + snprintf(tce.name, sizeof(tce.name), "%s:%d", + kbasename(node->parent->full_name), channel); + tce.clkevt.cpumask = cpumask_of(0); + tce.clkevt.name = tce.name; + tce.clkevt.set_next_event = tc_clkevt2_next_event, + tce.clkevt.set_state_shutdown = tc_clkevt2_shutdown, + tce.clkevt.set_state_periodic = tc_clkevt2_set_periodic, + tce.clkevt.set_state_oneshot = tc_clkevt2_set_oneshot, + + /* try to enable clk to avoid future errors in mode change */ + ret = clk_prepare_enable(tce.clk); + if (ret) + goto err_slow; + clk_disable(tce.clk); + + clockevents_config_and_register(&tce.clkevt, 32768, 1, bits - 1); + + ret = request_irq(tce.irq, tc_clkevt2_irq, IRQF_TIMER | IRQF_SHARED, + tce.clkevt.name, &tce); + if (ret) + goto err_clk; + + tce.registered = true; + + return 0; + +err_clk: + clk_unprepare(tce.clk); +err_slow: + clk_disable_unprepare(tce.slow_clk); + + return ret; +} + static u64 tc_get_cycles(struct clocksource *cs) { u32 lower, upper, tmp; @@ -299,7 +460,7 @@ static int __init tcb_clksrc_init(struct device_node *node) u32 channel; int bits, irq, err, chan1 = -1; - if (tc.registered) + if (tc.registered && tce.registered) return -ENODEV; regmap = syscon_node_to_regmap(node->parent); @@ -318,12 +479,20 @@ static int __init tcb_clksrc_init(struct device_node *node) if (irq < 0) return irq; + if (tc.registered) + return tc_clkevt_register(node, regmap, channel, irq, bits); + if (bits == 16) { of_property_read_u32_index(node, "reg", 1, &chan1); if (chan1 == -1) { - pr_err("%s: clocksource needs two channels\n", - node->parent->full_name); - return -EINVAL; + if (tce.registered) { + pr_err("%s: clocksource needs two channels\n", + node->parent->full_name); + return -EINVAL; + } else { + return tc_clkevt_register(node, regmap, channel, + irq, bits); + } } }