From patchwork Wed Jun 7 21:27:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 9772871 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 07A346034B for ; Wed, 7 Jun 2017 21:28:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 176D02843F for ; Wed, 7 Jun 2017 21:28:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0C2CF2848F; Wed, 7 Jun 2017 21:28:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 95ECB2843F for ; Wed, 7 Jun 2017 21:28:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xHnpzBDym65AoSXuVKt0YMUfVGez3DuPz2W49+SV3xE=; b=l7TO2NPP6yZHN7 gfA1rtKZmHneXvYbK+DPXc3wRWYYOgvPPwcYfUqAKrK+D/eSYO+ymrBlY10Im+VRn9V/XFba7OsGD dtosqBuSVkInQum2pLfCOoCZvSgkhfRVJYajklBTI1hBmrT+K1m/mNkr+FYh1+wSO4rQI3kh01EFT Sn+KK772Y2QdvBIhdskJjKw85oskNyu379FeKxiX2UXuoB/fyFyBC9VCFC/M+Nb47yb36Aeix0+Ep pJ4+gK7W8HB7bZef+1z4f8fTFgfvkdrO3bj+L5X4JGXiblwuYfkMGtmoLxsyZdSJfLZHcPh3938tw /FhWdQ4nk3EcPsLl+v1w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dIiUt-00005B-Cr; Wed, 07 Jun 2017 21:28:11 +0000 Received: from lelnx193.ext.ti.com ([198.47.27.77]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dIiUg-0008Im-9e for linux-arm-kernel@lists.infradead.org; Wed, 07 Jun 2017 21:27:59 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v57LRXtK029829; Wed, 7 Jun 2017 16:27:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1496870853; bh=XskRseTFiiumbEDOCRVE9DhX/AJS8JoW7FNcwV+XO2g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Fyvxj2OFWdm/I0mrVqMIRpdCBpcqr0iE0GbUNsat6oZnp/e6q6xVPEv1HeVJ1qOBX Zo44B+DYSKTO/d2+S7GOldUQcXOQ34GTkb/6qENJWsVIZkfclyvEcI5Bxr7Rv9heTk Rukew4vGdXBiY0zLg+pWWi+/cdlfbRMxKwjhuE/4= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRXOa003998; Wed, 7 Jun 2017 16:27:33 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Wed, 7 Jun 2017 16:27:32 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRWBL015971; Wed, 7 Jun 2017 16:27:33 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.167]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v57LRW307114; Wed, 7 Jun 2017 16:27:32 -0500 (CDT) From: Suman Anna To: Tony Lindgren Subject: [PATCH 4/6] ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates Date: Wed, 7 Jun 2017 16:27:28 -0500 Message-ID: <20170607212730.33002-5-s-anna@ti.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> References: <20170607212730.33002-1-s-anna@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170607_142758_429854_81075E57 X-CRM114-Status: UNSURE ( 9.24 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Lokesh Vutla , Tero Kristo , Subhajit Paul , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The DSP DPLL is a new DPLL compared to previous OMAP generations and supplies the root clocks for the DSP processors, as well as a mux input source for EVE sub-system (on applicable SoCs). This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the DSP DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The DSP DPLL provides two output clocks, DSP_GFCLK and EVE_GCLK. The desired rate for DSP_GFCLK is 600 MHz (same as DSP DPLL CLKOUT frequency), and is currently auto set due to the desired M2 divider value being the same as reset value for the locked frequency of 600 MHz. The EVE_GCLK however is required to be 400 MHz, so set the dpll_dsp_m3x2_ck's rate explicitly so that the divider is set properly. The dpll_dsp_m2_ck rate is also set explicitly to not rely on any implicit matching divider reset values to the locked DPLL frequency. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 1200 MHz, so the dpll_dsp_ck clock rate used is half of this value. Signed-off-by: Suman Anna --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index cfaf27215901..8a82490035d9 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -338,6 +338,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; + assigned-clocks = <&dpll_dsp_ck>; + assigned-clock-rates = <600000000>; }; dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { @@ -349,6 +351,8 @@ reg = <0x0244>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m2_ck>; + assigned-clock-rates = <600000000>; }; iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { @@ -659,6 +663,8 @@ reg = <0x0248>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m3x2_ck>; + assigned-clock-rates = <400000000>; }; dpll_gmac_x2_ck: dpll_gmac_x2_ck {