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bh=qAHpPC294+j2FQClJAGOp5VWTfrHNN/3FmBsdIDubRo=; b=CAS/ZtM+WG7kHg8yy3+ypU6hi3Q2a896pEXRfOaP2AO/UDweNkHGa5sFsHPlf9Deiv FLGx+aPoYFJL2JZmx3A8UhvGR2iT8mYdIMR00HCScOpF3wSyretKaIXLIKwOU5vnEH8T yjlxUnWA2fQ0mp8C8h6gY6OvJRft87FOyqKDmhxGI0Sh9dbeiia8HIbFu7prEmmCCqNN 78pUdsvcIE9BbfsIA82/N7OndU542dmnscGN+qbtCZtN6wC66XDdQyOGdTUIsDKve9KM 5aumXa5Hle8BGoKmShNXJol93k9c44EFAH/Aw0F3IfwJO95WvKxiahHJlW3HZc1reh8C u1kw== X-Gm-Message-State: AKS2vOxEXV+bXtenHKvhFmf6Nzac0HHWF41SYK0g/MxPav8C4qtz/FcM 9rUrCJyQCWEzQXOi53w= X-Received: by 10.80.143.36 with SMTP id 33mr8298903edy.68.1498661882642; Wed, 28 Jun 2017 07:58:02 -0700 (PDT) Received: from localhost.localdomain ([2a02:a03f:837:f300:dc41:f6b3:4608:d7c8]) by smtp.gmail.com with ESMTPSA id p19sm1517099eda.15.2017.06.28.07.58.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Jun 2017 07:58:02 -0700 (PDT) From: Luc Van Oostenryck To: Will Deacon Subject: [PATCH] arm64: fix endianness annotation for reloc_insn_movw() & reloc_insn_imm() Date: Wed, 28 Jun 2017 16:56:00 +0200 Message-Id: <20170628145600.24498-1-luc.vanoostenryck@gmail.com> X-Mailer: git-send-email 2.13.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170628_075824_517712_608C1E2D X-CRM114-Status: GOOD ( 12.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Catalin Marinas , Florian Fainelli , Luc Van Oostenryck , linux-arm-kernel@lists.infradead.org, Ard Biesheuvel MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Here the functions reloc_insn_movw() & reloc_insn_imm() are used to read, modify and write back ARM instructions, which are always stored in memory in little-endian order. These values are thus correctly converted to/from native order but the pointers used to hold their addresses are declared as for native order values. Fix this by declaring the pointers as __le32* and remove the casts that are now unneeded. Signed-off-by: Luc Van Oostenryck --- arch/arm64/kernel/module.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c index f035ff6fb..864725d9e 100644 --- a/arch/arm64/kernel/module.c +++ b/arch/arm64/kernel/module.c @@ -74,7 +74,7 @@ enum aarch64_reloc_op { RELOC_OP_PAGE, }; -static u64 do_reloc(enum aarch64_reloc_op reloc_op, void *place, u64 val) +static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val) { switch (reloc_op) { case RELOC_OP_ABS: @@ -121,12 +121,12 @@ enum aarch64_insn_movw_imm_type { AARCH64_INSN_IMM_MOVKZ, }; -static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val, +static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val, int lsb, enum aarch64_insn_movw_imm_type imm_type) { u64 imm; s64 sval; - u32 insn = le32_to_cpu(*(u32 *)place); + u32 insn = le32_to_cpu(*place); sval = do_reloc(op, place, val); imm = sval >> lsb; @@ -154,7 +154,7 @@ static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val, /* Update the instruction with the new encoding. */ insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm); - *(u32 *)place = cpu_to_le32(insn); + *place = cpu_to_le32(insn); if (imm > U16_MAX) return -ERANGE; @@ -162,12 +162,12 @@ static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val, return 0; } -static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val, +static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val, int lsb, int len, enum aarch64_insn_imm_type imm_type) { u64 imm, imm_mask; s64 sval; - u32 insn = le32_to_cpu(*(u32 *)place); + u32 insn = le32_to_cpu(*place); /* Calculate the relocation value. */ sval = do_reloc(op, place, val); @@ -179,7 +179,7 @@ static int reloc_insn_imm(enum aarch64_reloc_op op, void *place, u64 val, /* Update the instruction's immediate field. */ insn = aarch64_insn_encode_immediate(imm_type, insn, imm); - *(u32 *)place = cpu_to_le32(insn); + *place = cpu_to_le32(insn); /* * Extract the upper value bits (including the sign bit) and