From patchwork Tue Jul 25 15:55:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 9862469 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 03BDF601A1 for ; Tue, 25 Jul 2017 15:57:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E901D286F7 for ; Tue, 25 Jul 2017 15:57:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DD51D286F9; Tue, 25 Jul 2017 15:57:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 325FA286F7 for ; Tue, 25 Jul 2017 15:57:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=W9cNdpJRNc7F4bTT0quQVdCgAUIC7WfxwWCzgGQiC6M=; b=pfLrVK4TybhgGC7xMV4DCefk8e hY1fXEKDwqQoNIBGhvB1wxY6PYI7lk6466b9G/R2Huyt6gOyTkFICkrYoqw83Y2r3m4esmvmyTagQ q8wYqnxc2/mvNt/RzjtyeQl5Wn0P+pHyN1NcfrbUX9+nTqYam3xP0KPZBkDEG5WfLqDm6UZ3c4ZMN 2E/DGrGuP5y9XpKOY0bDUupU2sxToisk5E5hui/xpHPd/19ywmgjAskzHhUHv3fP1BRTVdIgVYn/a 91eBMQShpknIXPnB9qaKtfvcMhK87RNPLpHYFnMmqxh+5K2+NElZpTyRSQSDxtfb1OQnzC56wPBUq oTZYNIQw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1da2DO-0004TM-UU; Tue, 25 Jul 2017 15:57:42 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1da2C4-0002hE-8t for linux-arm-kernel@bombadil.infradead.org; Tue, 25 Jul 2017 15:56:20 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=1jcfvk2B31dedPBu9B65o1h7KqMuz2qwCfqevzFzqZI=; b=Ipix6F+26jCYk6k6GK6mCVv9I sCYVOTb0fO/TYmCJ/i11UCygjyTRc+e3tor6Vg/py+8VK36EO4LwJQN97TZYOs6BJJpVLXnnkoVo5 Ywb/o8+IAL/Fglwc9oGaexliKxTcdnyXx2xLnbapc6fBJo19whr4jwLMaNkD4PKV7tSgNLu1yd6f9 Q/wgLMDyBkBODM/iMmu8S+RMwKIxn+HzLwVVoLrUxIEeQc14vtD9sM9JyAwgICAUBG7682LpeRuAk exMUjTBfUo25q5GPFJlc4ukhJ+IQw1T8Hye5e/zA0GZlZop8dwj4GPIkm6E9tQlfw+6Iq9YNkVy2b Aba2kBilQ==; Received: from mail.free-electrons.com ([62.4.15.54]) by casper.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1da2Bg-0001z1-8D for linux-arm-kernel@lists.infradead.org; Tue, 25 Jul 2017 15:55:57 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id 6313120900; Tue, 25 Jul 2017 17:55:38 +0200 (CEST) Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 5EF3121DDC; Tue, 25 Jul 2017 17:55:19 +0200 (CEST) From: Thomas Petazzoni To: netdev@vger.kernel.org, "David S. Miller" Subject: [PATCH 4/8] net: mvpp2: move from cpu-centric naming to "software thread" naming Date: Tue, 25 Jul 2017 17:55:05 +0200 Message-Id: <20170725155509.10574-5-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170725155509.10574-1-thomas.petazzoni@free-electrons.com> References: <20170725155509.10574-1-thomas.petazzoni@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170725_165556_314643_6C5B71FD X-CRM114-Status: GOOD ( 23.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Petazzoni , Andrew Lunn , Yehuda Yitschak , Russell King , Jason Cooper , Antoine Tenart , Nadav Haklai , =?UTF-8?q?Miqu=C3=A8l=20Raynal?= , Gregory Clement , Stefan Chulski , Marcin Wojtas , Hanna Hawa , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The PPv2.2 IP has a concept of "software thread", with all registers of the PPv2.2 mapped 8 times, for concurrent accesses by 8 "software threads". In addition, interrupts on RX queues are associated to such "software thread". For most cases, we map a "software thread" to the more conventional concept of CPU, but we will soon have one exception: we will have a model where we have one TX interrupt per CPU (each using one software thread), and all RX events mapped to another software thread (associated to another interrupt). In preparation for this change, it makes sense to change the naming from MVPP2_MAX_CPUS to MVPP2_MAX_THREADS, and plan for 8 software threads instead of 4 currently. Signed-off-by: Thomas Petazzoni --- drivers/net/ethernet/marvell/mvpp2.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index 8479269..7d37869 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -748,7 +748,7 @@ enum mvpp2_prs_l3_cast { #define MVPP21_ADDR_SPACE_SZ 0 #define MVPP22_ADDR_SPACE_SZ SZ_64K -#define MVPP2_MAX_CPUS 4 +#define MVPP2_MAX_THREADS 8 enum mvpp2_bm_type { MVPP2_BM_FREE, @@ -764,11 +764,12 @@ struct mvpp2 { void __iomem *lms_base; void __iomem *iface_base; - /* On PPv2.2, each CPU can access the base register through a - * separate address space, each 64 KB apart from each - * other. + /* On PPv2.2, each "software thread" can access the base + * register through a separate address space, each 64 KB apart + * from each other. Typically, such address spaces will be + * used per CPU. */ - void __iomem *cpu_base[MVPP2_MAX_CPUS]; + void __iomem *swth_base[MVPP2_MAX_THREADS]; /* On PPv2.2, some port control registers are located into the system * controller space. These registers are accessible through a regmap. @@ -1140,12 +1141,12 @@ struct mvpp2_bm_pool { static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) { - writel(data, priv->cpu_base[0] + offset); + writel(data, priv->swth_base[0] + offset); } static u32 mvpp2_read(struct mvpp2 *priv, u32 offset) { - return readl(priv->cpu_base[0] + offset); + return readl(priv->swth_base[0] + offset); } /* These accessors should be used to access: @@ -1187,13 +1188,13 @@ static u32 mvpp2_read(struct mvpp2 *priv, u32 offset) static void mvpp2_percpu_write(struct mvpp2 *priv, int cpu, u32 offset, u32 data) { - writel(data, priv->cpu_base[cpu] + offset); + writel(data, priv->swth_base[cpu] + offset); } static u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu, u32 offset) { - return readl(priv->cpu_base[cpu] + offset); + return readl(priv->swth_base[cpu] + offset); } static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, @@ -7282,7 +7283,7 @@ static int mvpp2_probe(struct platform_device *pdev) struct mvpp2 *priv; struct resource *res; void __iomem *base; - int port_count, cpu; + int port_count, i; int err; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); @@ -7320,12 +7321,12 @@ static int mvpp2_probe(struct platform_device *pdev) priv->sysctrl_base = NULL; } - for_each_present_cpu(cpu) { + for (i = 0; i < MVPP2_MAX_THREADS; i++) { u32 addr_space_sz; addr_space_sz = (priv->hw_version == MVPP21 ? MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); - priv->cpu_base[cpu] = base + cpu * addr_space_sz; + priv->swth_base[i] = base + i * addr_space_sz; } if (priv->hw_version == MVPP21)