From patchwork Tue Aug 1 04:54:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 9873669 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 10B826038F for ; Tue, 1 Aug 2017 05:00:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0443C2863C for ; Tue, 1 Aug 2017 05:00:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ED55B2863E; Tue, 1 Aug 2017 05:00:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6FE0D28645 for ; Tue, 1 Aug 2017 05:00:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wjzaeQAAWLSRrB5t6CfEm6Uk/uKdgBdn5xTAUeIjw+U=; b=sGrn3jG5v/hbnr NqcuJMxy3z4VQA08hCmUWtx6lj9fgZL7j/Y82p4O/sG5NjmtQdcHGeItmAKtMDCEnn4sgg7mRCcvK QvoJ3bs7A3a3hblxNkJAaihdgTnZey/8IMGYm3uBuUQUNjU0L0G6+C4BigjrCWqT+sCpwU84fksxv a0n+bxN+a0xha0QlGkVAmBiYlIvEagfZiaa8oIeS6uHdjB9FWtmhMHhTJyzK4mnTnaX2/GzuBci50 elt8jgjJoaVYCMU5viRvUla7i1xvnnkBu1P77UL3qCNi9EoTLev9FWZ42wxXepb/U73MzTPMueuwD ARKaaoYJgV5U5/atLArg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dcPHk-0005sE-2K; Tue, 01 Aug 2017 05:00:00 +0000 Received: from fllnx209.ext.ti.com ([198.47.19.16]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dcPDv-0001sj-4v; Tue, 01 Aug 2017 04:56:48 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v714sZ3p015038; Mon, 31 Jul 2017 23:54:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1501563275; bh=OvispDuyMLD+w+bVafBM0tOuzJkRFb6JGvjo/FWnqmg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JmzEKjV603NMTxZ9TLgVQhQGqs13fzv0l80xGi3iFCctwkPXQt/abLqZiYHd4IfvO IwXKOzWlfWCbO2hrnbkdCRDa9VCbbL6OEhPSBr/6jZP+lp2LbBM07nN48ESYs0+Rvn LI7SVZucWQeImGDt9cu7g32jSh7cU7ZlWWGz0Yis= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v714sUbU027395; Mon, 31 Jul 2017 23:54:30 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 31 Jul 2017 23:54:29 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v714sN9G027903; Mon, 31 Jul 2017 23:54:27 -0500 From: Vignesh R To: Marek Vasut , Cyrille Pitchen , Rob Herring , Santosh Shilimkar Subject: [PATCH 1/7] mtd: spi-nor: cadence-quadspi: add a delay in write sequence Date: Tue, 1 Aug 2017 10:24:28 +0530 Message-ID: <20170801045434.8733-2-vigneshr@ti.com> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170801045434.8733-1-vigneshr@ti.com> References: <20170801045434.8733-1-vigneshr@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170731_215604_928910_38257084 X-CRM114-Status: GOOD ( 12.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Vignesh R , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Brian Norris , David Woodhouse , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay equal to couple QSPI master clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and writing data to the flash. Add a new compatible to handle the couple of cycles of delay required in the indirect write sequence, since this delay is specific to TI 66AK2G SoC. [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf Signed-off-by: Vignesh R --- Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 1 + drivers/mtd/spi-nor/cadence-quadspi.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt index f248056da24c..fdd511a83511 100644 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt @@ -2,6 +2,7 @@ Required properties: - compatible : Should be "cdns,qspi-nor". + Should be "ti,k2g-qspi" for TI 66AK2G platform. - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 53c7d8e0327a..94571590371d 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -76,6 +76,7 @@ struct cqspi_st { u32 fifo_depth; u32 fifo_width; u32 trigger_address; + u32 wr_delay; struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; }; @@ -608,6 +609,14 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor, reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTWR_START_MASK, reg_base + CQSPI_REG_INDIRECTWR); + /* + * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access + * Controller programming sequence, couple of cycles of + * QSPI_REF_CLK delay is required for the above bit to + * be internally synchronized by the QSPI module. Provide 5 + * cycles of delay. + */ + ndelay(cqspi->wr_delay); while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining; @@ -1213,6 +1222,9 @@ static int cqspi_probe(struct platform_device *pdev) } cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); + if (of_device_is_compatible(dev->of_node, "ti,k2g-qspi")) + cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, + cqspi->master_ref_clk_hz); ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, pdev->name, cqspi); @@ -1285,6 +1297,7 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = { static const struct of_device_id cqspi_dt_ids[] = { {.compatible = "cdns,qspi-nor",}, + {.compatible = "ti,k2g-qspi",}, { /* end of table */ } };