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Sun, 20 Aug 2017 10:21:24 +0000 From: Yury Norov To: Catalin Marinas , Pratyush Anand Subject: [PATCH 1/2] arm64: introduce separated bits for mm_context_t flags Date: Sun, 20 Aug 2017 13:20:47 +0300 Message-Id: <20170820102048.7537-2-ynorov@caviumnetworks.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170820102048.7537-1-ynorov@caviumnetworks.com> References: <20170820102048.7537-1-ynorov@caviumnetworks.com> MIME-Version: 1.0 X-Originating-IP: [88.148.44.91] X-ClientProxiedBy: HE1PR06CA0145.eurprd06.prod.outlook.com (10.170.251.32) To CY1PR07MB2120.namprd07.prod.outlook.com (10.164.73.158) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bdbdc44c-7f1b-405c-bca7-08d4e7b536bf X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(300000503095)(300135400095)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); 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For example, mm_context_t doesn't need most of thread_info flags. And it would be difficult to add new mm-related flag if needed because it may easily interfere with TIF ones. To deal with it, the new MMCF_AARCH32 flag is introduced for mm_context_t->flags, where MMCF prefix stands for mm_context_t flags. Also, mm_context_t flag doesn't require atomicity and ordering of the access, so using set/clear_bit() is replaced with simple masks. RFC: https://lkml.org/lkml/2017/7/31/454 v1: - changed the MMCF_AARCH32 bit number from 0x1 to 0x0 and added comment v2: - using set/clear_bit() is replaced with simple masks. Signed-off-by: Yury Norov --- arch/arm64/include/asm/elf.h | 4 ++-- arch/arm64/include/asm/mmu.h | 2 ++ arch/arm64/kernel/probes/uprobes.c | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h index 3288c2b36731..517b9ff0456c 100644 --- a/arch/arm64/include/asm/elf.h +++ b/arch/arm64/include/asm/elf.h @@ -139,7 +139,7 @@ typedef struct user_fpsimd_state elf_fpregset_t; #define SET_PERSONALITY(ex) \ ({ \ - clear_bit(TIF_32BIT, ¤t->mm->context.flags); \ + current->mm->context.flags = 0; \ clear_thread_flag(TIF_32BIT); \ current->personality &= ~READ_IMPLIES_EXEC; \ }) @@ -195,7 +195,7 @@ typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG]; */ #define COMPAT_SET_PERSONALITY(ex) \ ({ \ - set_bit(TIF_32BIT, ¤t->mm->context.flags); \ + current->mm->context.flags = MMCF_AARCH32; \ set_thread_flag(TIF_32BIT); \ }) #define COMPAT_ARCH_DLINFO diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index 5468c834b072..e4c474c6501e 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -16,6 +16,8 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H +#define MMCF_AARCH32 0x1 /* MM hosts AArch32 executables */ + typedef struct { atomic64_t id; void *vdso; diff --git a/arch/arm64/kernel/probes/uprobes.c b/arch/arm64/kernel/probes/uprobes.c index 26c998534dca..636ca0119c0e 100644 --- a/arch/arm64/kernel/probes/uprobes.c +++ b/arch/arm64/kernel/probes/uprobes.c @@ -40,7 +40,7 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, probe_opcode_t insn; /* TODO: Currently we do not support AARCH32 instruction probing */ - if (test_bit(TIF_32BIT, &mm->context.flags)) + if (mm->context.flags & MMCF_AARCH32) return -ENOTSUPP; else if (!IS_ALIGNED(addr, AARCH64_INSN_SIZE)) return -EINVAL;