From patchwork Mon Aug 21 23:48:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 9913993 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5DB30602B1 for ; Mon, 21 Aug 2017 23:55:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4B4DF286B5 for ; Mon, 21 Aug 2017 23:55:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3FF01286EF; Mon, 21 Aug 2017 23:55:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C84C128709 for ; Mon, 21 Aug 2017 23:55:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RmtOeRiWrwU8mBbKJ4ychjJ0izoVitG3cPgybrj/YKU=; b=Pqy10FXiLK5TdW xwQVZLsZRBfUsZ00lukhXUKNqdlx1+McXu41OzYjGZ17a2QlIH4CXE+fU3o5XwnCZGCz+5gNeNm5L zrJR1eJ9UPs36hiMR26jfUUSO/yBMkqxMEIIPh46VQjitMtsymkQ1ZjyFCR5NEFKutL9nLuCZ6vt1 3Otno6PfBZPpqN3PH7MvXtGqxjTFzopc6oTl9c4FAQ/E9W/mngHygVBesgewnbQaV4oz1UEW4elaU GJEo9Rl4QDo4QAL54ylQUnS0g72gu50dskZiOkeVdmCPb08TxPRQxyIpnln2vQWcBovoKoGRH5t33 I+x+KEL2Jg1+vkKLV1TQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1djwXL-0008DE-SR; Mon, 21 Aug 2017 23:55:15 +0000 Received: from lelnx193.ext.ti.com ([198.47.27.77]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1djwR3-00025N-01 for linux-arm-kernel@lists.infradead.org; Mon, 21 Aug 2017 23:48:49 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmL9H028091; Mon, 21 Aug 2017 18:48:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359301; bh=MYQgIAKyPSl2Amo3tRNJ0N9j5w+6+9gagJkxq/Ra64k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FPca4BYSLk86tNK/CBUiSIrUoGhyVdEFsf9wbDmH4pLbng30QaH+xOKMx0gtsR1Nm VWXzFwEwMCEDs3GNl5I6R0sZrlXrT0XfjQsOtdLMr+1qz47WXTNtkbUV9e3oHU2FZ3 zjjhhFm68C1c4UNf9rY7N0O0RF+CKFZKlRhKFx4s= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmL0f002318; Mon, 21 Aug 2017 18:48:21 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:21 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:21 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLU2032424; Mon, 21 Aug 2017 18:48:21 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmL307101; Mon, 21 Aug 2017 18:48:21 -0500 (CDT) From: Suman Anna To: Tony Lindgren Subject: [PATCH 6/8] ARM: OMAP5: hwmod_data: Add data for IPU & DSP processors Date: Mon, 21 Aug 2017 18:48:16 -0500 Message-ID: <20170821234818.4755-7-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170821_164845_194727_57D71B50 X-CRM114-Status: UNSURE ( 9.95 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tero Kristo , Paul Walmsley , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP OMAP5, like OMAP4, also has an IPU and a DSP processor subsystems. The relevant hwmod classes and data structures are added for these devices. Do note that these hwmod data strucutures do not have a .modulemode field as the devices are managed together with their corresponding MMUs. Each of the processor subsystem and its MMU are present within the same clock domain and requires the domain be clocked and enabled until the last entity is disabled. The module is disabled properly during the omap_device_idle processing of the MMU hwmod while disabling the MMU. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 79 ++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 9a67f013ebad..15f217b5e462 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -335,6 +335,36 @@ static struct omap_hwmod omap54xx_dmic_hwmod = { }; /* + * 'dsp' class + * dsp sub-system + */ + +static struct omap_hwmod_class omap54xx_dsp_hwmod_class = { + .name = "dsp", +}; + +static struct omap_hwmod_rst_info omap54xx_dsp_resets[] = { + { .name = "dsp", .rst_shift = 0 }, +}; + +/* dsp */ +static struct omap_hwmod omap54xx_dsp_hwmod = { + .name = "dsp", + .class = &omap54xx_dsp_hwmod_class, + .clkdm_name = "dsp_clkdm", + .rst_lines = omap54xx_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(omap54xx_dsp_resets), + .main_clk = "dpll_iva_h11x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET, + .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'dss' class * display sub-system */ @@ -940,6 +970,37 @@ static struct omap_hwmod omap54xx_i2c5_hwmod = { }; /* + * 'ipu' class + * image processor unit + */ + +static struct omap_hwmod_class omap54xx_ipu_hwmod_class = { + .name = "ipu", +}; + +static struct omap_hwmod_rst_info omap54xx_ipu_resets[] = { + { .name = "cpu0", .rst_shift = 0 }, + { .name = "cpu1", .rst_shift = 1 }, +}; + +/* ipu */ +static struct omap_hwmod omap54xx_ipu_hwmod = { + .name = "ipu", + .class = &omap54xx_ipu_hwmod_class, + .clkdm_name = "ipu_clkdm", + .rst_lines = omap54xx_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(omap54xx_ipu_resets), + .main_clk = "dpll_core_h22x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET, + .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'kbd' class * keyboard controller */ @@ -2135,6 +2196,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* dsp -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap54xx_dsp__l3_main_1 = { + .master = &omap54xx_dsp_hwmod, + .slave = &omap54xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_cfg -> mmu_dsp */ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = { .master = &omap54xx_l4_cfg_hwmod, @@ -2167,6 +2236,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_2 -> ipu */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__ipu = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_ipu_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_2 -> mmu_ipu */ static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = { .master = &omap54xx_l3_main_2_hwmod, @@ -2766,7 +2843,9 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l3_main_3__l3_instr, &omap54xx_l3_main_2__l3_main_1, &omap54xx_l4_cfg__l3_main_1, + &omap54xx_dsp__l3_main_1, &omap54xx_mpu__l3_main_1, + &omap54xx_l3_main_2__ipu, &omap54xx_l3_main_1__l3_main_2, &omap54xx_l4_cfg__l3_main_2, &omap54xx_l3_main_1__l3_main_3,