| Message ID | 20170822170830.32413-11-antoine.tenart@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Antoine, On Tue, Aug 22, 2017 at 07:08:30PM +0200, Antoine Tenart wrote: > This patch enables the two GE/SFP ports. They are configured in 10GKR > mode by default. To do this the cpm_xdmio is enabled as well, and two > phy descriptions are added. > > Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> > Tested-by: Marcin Wojtas <mw@semihalf.com> > --- > arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 30 +++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts > index abd39d1c1739..6cb4b000e1ac 100644 > --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts > +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts > @@ -127,6 +127,30 @@ > }; > }; > > +&cpm_xmdio { > + status = "okay"; > + > + phy0: ethernet-phy@0 { > + compatible = "ethernet-phy-ieee802.3-c45"; > + reg = <0>; > + }; > + > + phy1: ethernet-phy@1 { Should be named 'ethernet-phy@8' to match the 'reg' property. > + compatible = "ethernet-phy-ieee802.3-c45"; > + reg = <8>; > + }; > +}; baruch
Hi Baruch, On Wed, Aug 23, 2017 at 10:28:42AM +0300, Baruch Siach wrote: > On Tue, Aug 22, 2017 at 07:08:30PM +0200, Antoine Tenart wrote: > > This patch enables the two GE/SFP ports. They are configured in 10GKR > > mode by default. To do this the cpm_xdmio is enabled as well, and two > > phy descriptions are added. > > > > Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> > > Tested-by: Marcin Wojtas <mw@semihalf.com> > > --- > > arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 30 +++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts > > index abd39d1c1739..6cb4b000e1ac 100644 > > --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts > > +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts > > @@ -127,6 +127,30 @@ > > }; > > }; > > > > +&cpm_xmdio { > > + status = "okay"; > > + > > + phy0: ethernet-phy@0 { > > + compatible = "ethernet-phy-ieee802.3-c45"; > > + reg = <0>; > > + }; > > + > > + phy1: ethernet-phy@1 { > > Should be named 'ethernet-phy@8' to match the 'reg' property. That's right. Thanks! Antoine
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts index abd39d1c1739..6cb4b000e1ac 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts @@ -127,6 +127,30 @@ }; }; +&cpm_xmdio { + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + }; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <8>; + }; +}; + +&cpm_ethernet { + status = "okay"; +}; + +&cpm_eth0 { + status = "okay"; + phy = <&phy0>; + phy-mode = "10gbase-kr"; +}; + &cpm_sata0 { /* CPM Lane 0 - U29 */ status = "okay"; @@ -154,6 +178,12 @@ status = "okay"; }; +&cps_eth0 { + status = "okay"; + phy = <&phy1>; + phy-mode = "10gbase-kr"; +}; + &cps_eth1 { /* CPS Lane 0 - J5 (Gigabit RJ45) */ status = "okay";