From patchwork Mon Aug 28 14:29:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 9925645 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 37EE660329 for ; Mon, 28 Aug 2017 14:31:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2538B20144 for ; Mon, 28 Aug 2017 14:31:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1A11F286D4; Mon, 28 Aug 2017 14:31:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_LOW autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 91A9020144 for ; Mon, 28 Aug 2017 14:31:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=NuBdfv3m0ZCQlsnAEn31UsA7h7NSPLrViEEHwIu2pOA=; b=ZbxnqTExDgrRk6QVtyX3Cif+OU HcsZcrCU4+oyoezjSAjh1flUinasXng2LZScluqi/IxgdikUjujxMsBagwHCrrlgDecSOJE+L1w4H mqhapkSqvLXq7Z+PWFP1ZXcYoEQ//K5E1uVVxcMZfxK39SwPe9LUwoZXFxMBhWD3TDVnHCXwpHrup suQhn7g5HL8xvPfjpxP00W9NaiaQlpUGkIvVDdvds/Yf8W4YD94NltElt8QZWhS4ORCmqwGkTiept fXQUvBYGUbgvxjA2s/9mOzRUpl+/JPPY1/b6QSPm2/oi/a2Ug97pvHtEsxa44/87o3c8vbQTNWhQz EhNMJF/w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dmL4O-0006iQ-GI; Mon, 28 Aug 2017 14:31:16 +0000 Received: from mail-wr0-x22c.google.com ([2a00:1450:400c:c0c::22c]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dmL2v-0004Wz-VC for linux-arm-kernel@lists.infradead.org; Mon, 28 Aug 2017 14:30:05 +0000 Received: by mail-wr0-x22c.google.com with SMTP id 40so1691679wrv.5 for ; Mon, 28 Aug 2017 07:29:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m2LavEGYkE6hveXQ402i8QyHI3Jw0kp2lrkRgTHjUds=; b=HcSlH7pM5y4Gn4msX+qV1eK2qjHFWI/qpmULfVsCtKVXdgpA0prvxmrCao26Momj5m QLJfRo+1OklEjZoNvq9ycy9Ag5yXyJcUaT2fCeWsdMx79Pa0ib/iyXMBt7F4DCoLm6D2 dEdyQwB8MMl/zxvgJbeuLfZkK4mTE9Hm+JRIfLfXVLy+JT0S1conHgoEhGMR0vuGRZ9f gq+rol9tcKw4hWS904omi9+xviFabfzj3AKtaon6zYY8y9e6Dcl23qlLBn7pKP8eb0w4 QvcHmbugHSjukNIEdx3/jmJQz4OyM/v+4/jaTQ00kR2tZ5Z1aCHHAR3u1o95A+p+x9hy D30A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m2LavEGYkE6hveXQ402i8QyHI3Jw0kp2lrkRgTHjUds=; b=qQoru1bjI9CA7pQmHEYN0mtaAEh938kscXt2uztzgWnqUgnkThvRQFSXaQbhH9gQ7s o+vMmC2rA/0Es0KsiRjNug3Jb6wFwnPpwkUJ2RvJ99HGhWhFr1xcJGN2OYfCZ9repb4j hg+bKDZ7sas7e6dPC4e98ZPmWe4Gb7zp4gxqFKF1X71OVZY1DYcf1Xf1RRtFnjJxcNTi kQ2vI1WyUzbAyoG4ge2Dyw5xpNRdIpFz7mJtGVAWBb2zh6kB8DzMbI6TtnmMTxV1mBbp XBRQWCtDq3RSNEV+nfeE3PyvgNKZismYNVS/sPBzikWXN7t0RoZyauw7JK5k7RoIqssc TMSw== X-Gm-Message-State: AHYfb5gLD/KxRxRNDoHJMGFg7vKFUIOU37tCS6jDmHBxVrSOg64KO+79 g1wDT33kVjFjGwtv X-Received: by 10.223.130.111 with SMTP id 102mr499604wrb.211.1503930565285; Mon, 28 Aug 2017 07:29:25 -0700 (PDT) Received: from localhost.localdomain (uluru.liltaz.com. [163.172.81.188]) by smtp.googlemail.com with ESMTPSA id z39sm604792wrz.61.2017.08.28.07.29.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Aug 2017 07:29:24 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Subject: [PATCH v3 06/13] mmc: meson-gx: fix dual data rate mode frequencies Date: Mon, 28 Aug 2017 16:29:08 +0200 Message-Id: <20170828142915.27020-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170828_072946_192089_879CEFF3 X-CRM114-Status: GOOD ( 14.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jerome Brunet MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In DDR modes, meson mmc controller requires an input rate twice as fast as the output rate Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Reviewed-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 41 +++++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 7800a7ace2de..341e5a1b32cc 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -262,14 +262,29 @@ static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, mmc_get_dma_dir(data)); } -static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) +static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios) +{ + if (ios->timing == MMC_TIMING_MMC_DDR52 || + ios->timing == MMC_TIMING_UHS_DDR50 || + ios->timing == MMC_TIMING_MMC_HS400) + return true; + + return false; +} + +static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) { struct mmc_host *mmc = host->mmc; + unsigned long rate = ios->clock; int ret; u32 cfg; + /* DDR modes require higher module clock */ + if (meson_mmc_timing_is_ddr(ios)) + rate <<= 1; + /* Same request - bail-out */ - if (host->req_rate == clk_rate) + if (host->req_rate == rate) return 0; /* stop clock */ @@ -278,25 +293,29 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate) writel(cfg, host->regs + SD_EMMC_CFG); host->req_rate = 0; - if (!clk_rate) { + if (!rate) { mmc->actual_clock = 0; /* return with clock being stopped */ return 0; } - ret = clk_set_rate(host->mmc_clk, clk_rate); + ret = clk_set_rate(host->mmc_clk, rate); if (ret) { dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", - clk_rate, ret); + rate, ret); return ret; } - host->req_rate = clk_rate; + host->req_rate = rate; mmc->actual_clock = clk_get_rate(host->mmc_clk); + /* We should report the real output frequency of the controller */ + if (meson_mmc_timing_is_ddr(ios)) + mmc->actual_clock >>= 1; + dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); - if (clk_rate != mmc->actual_clock) - dev_dbg(host->dev, "requested rate was %lu\n", clk_rate); + if (ios->clock != mmc->actual_clock) + dev_dbg(host->dev, "requested rate was %u\n", ios->clock); /* (re)start clock */ cfg = readl(host->regs + SD_EMMC_CFG); @@ -490,16 +509,14 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); val &= ~CFG_DDR; - if (ios->timing == MMC_TIMING_UHS_DDR50 || - ios->timing == MMC_TIMING_MMC_DDR52 || - ios->timing == MMC_TIMING_MMC_HS400) + if (meson_mmc_timing_is_ddr(ios)) val |= CFG_DDR; val &= ~CFG_CHK_DS; if (ios->timing == MMC_TIMING_MMC_HS400) val |= CFG_CHK_DS; - err = meson_mmc_clk_set(host, ios->clock); + err = meson_mmc_clk_set(host, ios); if (err) dev_err(host->dev, "Failed to set clock: %d\n,", err);