| Message ID | 20171012133019.17086-1-p.zabel@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Oct 12, 2017 at 10:30 AM, Philipp Zabel <p.zabel@pengutronix.de> wrote: > By default, the lcdif_pre_sel mux is switched to the pll3_pfd1_540m PFD > source. If this mux is allowed to propagate rate changes to its parent, > setting the LCDIF pixel clock rate to 9 MHz, as required by the LCD > panel, will cause the pll3_pfd1_540m PFD to be switched away from its > nominal rate to 288 MHz. > This has no negative side effects, as there are no other children to > this PFD. Still, to avoid surprises, it might be preferrable to switch > to the designated video PLL (pll5_video_div) as clock source for the > LCDIF pixel clock. > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Makes sense: Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
On Thu, Oct 12, 2017 at 03:30:19PM +0200, Philipp Zabel wrote: > By default, the lcdif_pre_sel mux is switched to the pll3_pfd1_540m PFD > source. If this mux is allowed to propagate rate changes to its parent, > setting the LCDIF pixel clock rate to 9 MHz, as required by the LCD > panel, will cause the pll3_pfd1_540m PFD to be switched away from its > nominal rate to 288 MHz. > This has no negative side effects, as there are no other children to > this PFD. Still, to avoid surprises, it might be preferrable to switch > to the designated video PLL (pll5_video_div) as clock source for the > LCDIF pixel clock. > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Applied, thanks.
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index 9c23e017d86ad..e5d3ef88be608 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -147,6 +147,8 @@ &lcdif { + assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
By default, the lcdif_pre_sel mux is switched to the pll3_pfd1_540m PFD source. If this mux is allowed to propagate rate changes to its parent, setting the LCDIF pixel clock rate to 9 MHz, as required by the LCD panel, will cause the pll3_pfd1_540m PFD to be switched away from its nominal rate to 288 MHz. This has no negative side effects, as there are no other children to this PFD. Still, to avoid surprises, it might be preferrable to switch to the designated video PLL (pll5_video_div) as clock source for the LCDIF pixel clock. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> --- arch/arm/boot/dts/imx6ul-14x14-evk.dts | 2 ++ 1 file changed, 2 insertions(+)