Message ID | 20171103093115.14915-4-xiaowei.bao@nxp.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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dmarc=fail action=none header.from=nxp.com; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1BFFO11OLC002.mail.protection.outlook.com (10.58.145.13) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.178.5 via Frontend Transport; Fri, 3 Nov 2017 09:50:01 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id vA39nNmS022617; Fri, 3 Nov 2017 02:49:53 -0700 From: Bao Xiaowei <xiaowei.bao@nxp.com> To: <robh+dt@kernel.org>, <mark.rutland@arm.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>, <bhelgaas@google.com>, <shawnguo@kernel.org>, <madalin.bucur@nxp.com>, <sumit.garg@nxp.com>, <yangbo.lu@nxp.com>, <hongtao.jia@nxp.com>, <Yuantian.Tang@nxp.com>, <leoyang.li@nxp.com>, <kishon@ti.com>, <jingoohan1@gmail.com>, <pbrobinson@gmail.com>, <songxiaowei@hisilicon.com>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>, <linuxppc-dev@lists.ozlabs.org>, <Zhiqiang.Hou@nxp.com>, <mingkai.hu@nxp.com>, <Minghuan.Lian@nxp.com> Subject: [PATCH 3/3] ARMv8: pcie: make the DWC EP driver support for layerscape Date: Fri, 3 Nov 2017 17:31:15 +0800 Message-ID: <20171103093115.14915-4-xiaowei.bao@nxp.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171103093115.14915-1-xiaowei.bao@nxp.com> References: <20171103093115.14915-1-xiaowei.bao@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131541762020778874; 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diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index 22ec82fcdea2..b5f507795779 100644 --- a/drivers/pci/dwc/Kconfig +++ b/drivers/pci/dwc/Kconfig @@ -108,6 +108,7 @@ config PCI_LAYERSCAPE depends on PCI_MSI_IRQ_DOMAIN select MFD_SYSCON select PCIE_DW_HOST + select PCIE_DW_EP help Say Y here if you want PCIe controller support on Layerscape SoCs.