From patchwork Tue Nov 7 10:47:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 10046457 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 00FAF60247 for ; Tue, 7 Nov 2017 11:06:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF56629CE0 for ; Tue, 7 Nov 2017 11:06:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C456029D03; Tue, 7 Nov 2017 11:06:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D2C4229CEC for ; Tue, 7 Nov 2017 11:06:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=wtpFnai6Lm4qn0T9kNeqL8mfjfarvppJgv8Xdcjx7X8=; b=NYwfI/s4gZMkgxYnBy6Rb0cfCA nenyzDjov8LYxtlaBeOiizllGxUs19hzulvCed+wmGfbnUYOj3EsXwtOTrz0dOJ4Bo9vceym8RYXR RUBNpjd/VTHrO9FZ3gj8Ls15hOskW/ouVTvYUW+rd7D5T/gwTNB3xyC/J7iUqJwqkaE5rhBPLdWLk ntjRvRVLqXx8miiWSnIAAYM8vzaYwQay15FHcbQ3q7RJAH9oh2tlUXnvULB279gyRC79pZYipF0K2 Ed4rRaJfKSi51fzMkA0Im0hA3VyDB4+U6RK1LFGiCXcsCkMzrPJlwUsxMBZB1B3k8AZHlJksS486r kbKyV95w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1eC1hl-0002Rm-H8; Tue, 07 Nov 2017 11:06:05 +0000 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1eC1Qu-0000x9-B9 for linux-arm-kernel@lists.infradead.org; Tue, 07 Nov 2017 10:48:48 +0000 Received: by mail-wm0-x243.google.com with SMTP id z3so2807799wme.5 for ; Tue, 07 Nov 2017 02:48:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=r+OQlXhumpYoaeIcYP/Aic87TmVylBF1D6yT03LQiA0=; b=d5N48W8LqTrIjaMVGcdoGyhaRDLgdL+jSl6rhaKq7+Owd9ObUyCizKZ+9N0apRK4Gl u3VvAWikix+uye0hlEuVmY5Wd4pDzBT4YH8HxKbBxcTmZVpo4wIarumi311QVVCfOAYi 5XEdFVHcxGceCdSMbKc8B6tjfi48H4hl1Ukow= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=r+OQlXhumpYoaeIcYP/Aic87TmVylBF1D6yT03LQiA0=; b=fMZrHIRjHgNLjOT3bVYGjN2vtqlKsz9LX7g2lIGjFNtW9000bzpPUDZBTas9p2RNUh RsoMofJDmmn5lPuKP3x+JbzqNBXjy2vlXvniSpWS7ipa7P38PYJFbGrW1F6SP6Xko2nv wdNi/wpjscd8NSA4XGJMYbjssfOC4i+06bZ1VTDnP2Yk7FO9N5AITYYdHNCcBb2NcrKY gGKnJXSWh2AEvfYLAP7oN+8bfCdil/xWPtAzc+xwD3K7tOmD55BY7uvRjrckZGXsFjOT RxzNyW6+qK9Cez8XnqztJ5zfk9a0Ip2fUHPKl/RodAege80BT0G2XKfAi3SH2aBeXz5D BXJQ== X-Gm-Message-State: AMCzsaUm2TMg0YqB/KMARU0PPCcsCbeTKkgeBlIbsg9/h235zvxqj58F Sm5X0me2Tzam3+f7iZMURUpDwQ== X-Google-Smtp-Source: ABhQp+TAlub2UqYrarRyTVZE2bvFWXaSZUeWWEgONtYU+PvpM/sc2MLecNZpFwwWkwG5YZz3e4WdTw== X-Received: by 10.80.151.186 with SMTP id e55mr24188463edb.91.1510051692671; Tue, 07 Nov 2017 02:48:12 -0800 (PST) Received: from localhost.localdomain (xd93dd96b.cust.hiper.dk. [217.61.217.107]) by smtp.gmail.com with ESMTPSA id q12sm1044958edj.29.2017.11.07.02.48.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Nov 2017 02:48:11 -0800 (PST) From: Christoffer Dall To: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= Subject: [PULL 02/26] arm64: Use physical counter for in-kernel reads when booted in EL2 Date: Tue, 7 Nov 2017 11:47:35 +0100 Message-Id: <20171107104800.30021-3-christoffer.dall@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171107104800.30021-1-christoffer.dall@linaro.org> References: <20171107104800.30021-1-christoffer.dall@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171107_024840_940713_64DBE511 X-CRM114-Status: GOOD ( 16.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Christoffer Dall , kvm@vger.kernel.org, Marc Zyngier , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Christoffer Dall Using the physical counter allows KVM to retain the offset between the virtual and physical counter as long as it is actively running a VCPU. As soon as a VCPU is released, another thread is scheduled or we start running userspace applications, we reset the offset to 0, so that userspace accessing the virtual timer can still read the virtual counter and get the same view of time as the kernel. This opens up potential improvements for KVM performance, but we have to make a few adjustments to preserve system consistency. Currently get_cycles() is hardwired to arch_counter_get_cntvct() on arm64, but as we move to using the physical timer for the in-kernel time-keeping on systems that boot in EL2, we should use the same counter for get_cycles() as for other in-kernel timekeeping operations. Similarly, implementations of arch_timer_set_next_event_phys() is modified to use the counter specific to the timer being programmed. VHE kernels or kernels continuing to use the virtual timer are unaffected. Cc: Will Deacon Cc: Mark Rutland Acked-by: Catalin Marinas Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm64/include/asm/timex.h | 2 +- drivers/clocksource/arm_arch_timer.c | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/timex.h b/arch/arm64/include/asm/timex.h index 81a076eb37fa..9ad60bae5c8d 100644 --- a/arch/arm64/include/asm/timex.h +++ b/arch/arm64/include/asm/timex.h @@ -22,7 +22,7 @@ * Use the current timer as a cycle counter since this is what we use for * the delay loop. */ -#define get_cycles() arch_counter_get_cntvct() +#define get_cycles() arch_timer_read_counter() #include diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index ff8f8a177156..061476e92db7 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -158,6 +158,7 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, * if we don't have the cp15 accessors we won't have a problem. */ u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; +EXPORT_SYMBOL_GPL(arch_timer_read_counter); static u64 arch_counter_read(struct clocksource *cs) { @@ -329,16 +330,19 @@ static void erratum_set_next_event_tval_generic(const int access, unsigned long struct clock_event_device *clk) { unsigned long ctrl; - u64 cval = evt + arch_counter_get_cntvct(); + u64 cval; ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); ctrl |= ARCH_TIMER_CTRL_ENABLE; ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; - if (access == ARCH_TIMER_PHYS_ACCESS) + if (access == ARCH_TIMER_PHYS_ACCESS) { + cval = evt + arch_counter_get_cntpct(); write_sysreg(cval, cntp_cval_el0); - else + } else { + cval = evt + arch_counter_get_cntvct(); write_sysreg(cval, cntv_cval_el0); + } arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); } @@ -913,7 +917,7 @@ static void __init arch_counter_register(unsigned type) /* Register the CP15 based counter if we have one */ if (type & ARCH_TIMER_TYPE_CP15) { - if (IS_ENABLED(CONFIG_ARM64) || + if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) || arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) arch_timer_read_counter = arch_counter_get_cntvct; else