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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id u7sm1714595wmf.15.2017.11.07.12.15.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Nov 2017 12:15:32 -0800 (PST) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, wens@csie.org Subject: [PATCH 2/2] ARM: sun8i: bananapi-m3: Enable dwmac-sun8i Date: Tue, 7 Nov 2017 21:13:26 +0100 Message-Id: <20171107201326.17401-2-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171107201326.17401-1-clabbe.montjoie@gmail.com> References: <20171107201326.17401-1-clabbe.montjoie@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171107_121555_231898_2CAFA895 X-CRM114-Status: UNSURE ( 9.55 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Corentin Labbe , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The dwmac-sun8i hardware is present on the bananapi m3 It uses an external PHY rtl8211e via RGMII. This patch create the needed emac and phy nodes. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index c606af3dbfed..45bdd5c17829 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -52,6 +52,7 @@ compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -88,6 +89,23 @@ /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */ }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + allwinner,rx-delay-ps = <700>; + allwinner,tx-delay-ps = <700>; + + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>;