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[80.210.64.78]) by smtp.gmail.com with ESMTPSA id f132sm3726885wmf.17.2017.11.20.11.16.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Nov 2017 11:16:55 -0800 (PST) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 8/8] KVM: arm/arm64: Avoid work when userspace iqchips are not used Date: Mon, 20 Nov 2017 20:16:49 +0100 Message-Id: <20171120191649.17290-9-christoffer.dall@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171120191649.17290-1-christoffer.dall@linaro.org> References: <20171120191649.17290-1-christoffer.dall@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171120_111718_433180_AD458D3C X-CRM114-Status: GOOD ( 15.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Eric Auger , Christoffer Dall , kvm@vger.kernel.org, Andre Przywara MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We currently check if the VM has a userspace irqchip on every exit from the VCPU, and if so, we do some work to ensure correct timer behavior. This is unfortunate, as we could avoid doing any work entirely, if we didn't have to support irqchip in userspace. Realizing the userspace irqchip on ARM is mostly a developer or hobby feature, and is unlikely to be used in servers or other scenarios where performance is a priority, we can use a refcounted static key to only check the irqchip configuration when we have at least one VM that uses an irqchip in userspace. Signed-off-by: Christoffer Dall --- virt/kvm/arm/arch_timer.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index bcde6bb99669..7b27316d4c3f 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -51,6 +51,8 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, struct arch_timer_context *timer_ctx); static bool kvm_timer_should_fire(struct arch_timer_context *timer_ctx); +static DEFINE_STATIC_KEY_FALSE(userspace_irqchip_in_use); + u64 kvm_phys_timer_read(void) { return timecounter->cc->read(timecounter->cc); @@ -563,7 +565,8 @@ static void unmask_vtimer_irq_user(struct kvm_vcpu *vcpu) */ void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) { - unmask_vtimer_irq_user(vcpu); + if (static_branch_unlikely(&userspace_irqchip_in_use)) + unmask_vtimer_irq_user(vcpu); } int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu) @@ -768,6 +771,8 @@ void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) soft_timer_cancel(&timer->bg_timer, &timer->expired); soft_timer_cancel(&timer->phys_timer, NULL); kvm_vgic_unmap_phys_irq(vcpu, vtimer->irq.irq); + if (timer->enabled && !irqchip_in_kernel(vcpu->kvm)) + static_branch_dec(&userspace_irqchip_in_use); } static bool timer_irqs_are_valid(struct kvm_vcpu *vcpu) @@ -821,8 +826,10 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) return 0; /* Without a VGIC we do not map virtual IRQs to physical IRQs */ - if (!irqchip_in_kernel(vcpu->kvm)) + if (!irqchip_in_kernel(vcpu->kvm)) { + static_branch_inc(&userspace_irqchip_in_use); goto no_vgic; + } if (!vgic_initialized(vcpu->kvm)) return -ENODEV;