From patchwork Wed Dec 27 22:14:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antoine Tenart X-Patchwork-Id: 10134103 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 52AB460318 for ; Wed, 27 Dec 2017 22:18:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 413B12BA9D for ; Wed, 27 Dec 2017 22:18:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 342892C38E; Wed, 27 Dec 2017 22:18:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B6C9F2BA9D for ; Wed, 27 Dec 2017 22:18:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=owWaJbfyZq5GicC5BQbIqpxfa4rKE8Ig8sz8brnYG7E=; b=tEAI6J5yDrvgICyZQJJj9nxlcs Bt9zlzqT9Mh/CFnwBiSOgRlgzUhqds5TSSI3paNuWHYLrHELprxV8UhPkV5drTby2If/8hxxcUq2A QVLHp1FhFU1Ua02iaRxJYf5qYxuGt4v0FMopmMY9OHvFtdQ35wplyjhy0Zra1xiJddL8vEBkj9Ur3 obTF2dyfHME3q5iDfeikVePryyRaPS/uy7VpN8vivkk2vpr3QQAtArxYLtZB2gzT+PLN1CccRQMgU us+XIwlSvMRPgiFqd+p35QzO2sZBGN4GO2Q+5Sh7HxMmoJMTYLGxcImHGd7CIvBh+YgtiOfmaI4zW 3S7S9bAQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1eUK1t-00066G-F1; Wed, 27 Dec 2017 22:18:29 +0000 Received: from mail.free-electrons.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1eUJz0-0004KA-FH for linux-arm-kernel@lists.infradead.org; Wed, 27 Dec 2017 22:15:47 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id E4E7B20733; Wed, 27 Dec 2017 23:15:07 +0100 (CET) Received: from localhost (lac60-1-78-202-55-202.fbx.proxad.net [78.202.55.202]) by mail.free-electrons.com (Postfix) with ESMTPSA id 8D0C52072B; Wed, 27 Dec 2017 23:15:07 +0100 (CET) From: Antoine Tenart To: davem@davemloft.net, kishon@ti.com, andrew@lunn.ch, jason@lakedaemon.net, sebastian.hesselbarth@gmail.com, gregory.clement@free-electrons.com, linux@armlinux.org.uk Subject: [PATCH net-next 3/6] net: mvpp2: 1000baseX support Date: Wed, 27 Dec 2017 23:14:43 +0100 Message-Id: <20171227221446.18459-4-antoine.tenart@free-electrons.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171227221446.18459-1-antoine.tenart@free-electrons.com> References: <20171227221446.18459-1-antoine.tenart@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171227_141531_383227_718F45D0 X-CRM114-Status: GOOD ( 13.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thomas.petazzoni@free-electrons.com, ymarkman@marvell.com, netdev@vger.kernel.org, Antoine Tenart , linux-kernel@vger.kernel.org, nadavh@marvell.com, miquel.raynal@free-electrons.com, stefanc@marvell.com, mw@semihalf.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the 1000Base-X PHY mode support in the Marvell PPv2 driver. 1000Base-X is quite close the SGMII and uses nearly the same code path. Signed-off-by: Antoine Tenart --- drivers/net/ethernet/marvell/mvpp2.c | 45 ++++++++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index a19760736b71..094db9dd633f 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -4501,6 +4501,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port) mvpp22_gop_init_rgmii(port); break; case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: mvpp22_gop_init_sgmii(port); break; case PHY_INTERFACE_MODE_10GKR: @@ -4538,7 +4539,8 @@ static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) u32 val; if (phy_interface_mode_is_rgmii(port->phy_interface) || - port->phy_interface == PHY_INTERFACE_MODE_SGMII) { + port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { /* Enable the GMAC link status irq for this port */ val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; @@ -4568,7 +4570,8 @@ static void mvpp22_gop_mask_irq(struct mvpp2_port *port) } if (phy_interface_mode_is_rgmii(port->phy_interface) || - port->phy_interface == PHY_INTERFACE_MODE_SGMII) { + port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); @@ -4580,7 +4583,8 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port) u32 val; if (phy_interface_mode_is_rgmii(port->phy_interface) || - port->phy_interface == PHY_INTERFACE_MODE_SGMII) { + port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { val = readl(port->base + MVPP22_GMAC_INT_MASK); val |= MVPP22_GMAC_INT_MASK_LINK_STAT; writel(val, port->base + MVPP22_GMAC_INT_MASK); @@ -4605,6 +4609,7 @@ static int mvpp22_comphy_init(struct mvpp2_port *port) switch (port->phy_interface) { case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: mode = PHY_MODE_SGMII; break; case PHY_INTERFACE_MODE_10GKR: @@ -4625,7 +4630,8 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port) { u32 val; - if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) { + if (port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { val = readl(port->base + MVPP22_GMAC_CTRL_4_REG); val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL | MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; @@ -4640,9 +4646,11 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port) writel(val, port->base + MVPP22_GMAC_CTRL_4_REG); } - /* The port is connected to a copper PHY */ val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); - val &= ~MVPP2_GMAC_PORT_TYPE_MASK; + if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) + val |= MVPP2_GMAC_PORT_TYPE_MASK; + else + val &= ~MVPP2_GMAC_PORT_TYPE_MASK; writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); @@ -4651,6 +4659,19 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port) MVPP2_GMAC_AN_DUPLEX_EN; if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) val |= MVPP2_GMAC_IN_BAND_AUTONEG; + + if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) + /* 1000BaseX port cannot negotiate speed nor can it + * negotiate duplex: they are always operating with a + * fixed speed of 1000Mbps in full duplex, so force + * 1000 speed and full duplex here. + */ + val |= MVPP2_GMAC_CONFIG_GMII_SPEED | + MVPP2_GMAC_CONFIG_FULL_DUPLEX; + else + val |= MVPP2_GMAC_AN_SPEED_EN | + MVPP2_GMAC_AN_DUPLEX_EN; + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); } @@ -4671,7 +4692,8 @@ static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port) /* Configure the PCS and in-band AN */ val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); - if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) { + if (port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK; } else if (phy_interface_mode_is_rgmii(port->phy_interface)) { val &= ~MVPP2_GMAC_PCS_ENABLE_MASK; @@ -4733,7 +4755,8 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port) mvpp22_port_mii_set(port); if (phy_interface_mode_is_rgmii(port->phy_interface) || - port->phy_interface == PHY_INTERFACE_MODE_SGMII) + port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { mvpp2_port_mii_gmac_configure(port); else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR) mvpp2_port_mii_xlg_configure(port); @@ -4810,7 +4833,8 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port) else val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; - if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) + if (port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) val |= MVPP2_GMAC_PCS_LB_EN_MASK; else val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; @@ -6023,7 +6047,8 @@ static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id) link = true; } } else if (phy_interface_mode_is_rgmii(port->phy_interface) || - port->phy_interface == PHY_INTERFACE_MODE_SGMII) { + port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { val = readl(port->base + MVPP22_GMAC_INT_STAT); if (val & MVPP22_GMAC_INT_STAT_LINK) { event = true;