From patchwork Mon Jan 8 14:26:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 10149663 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 65B95602CA for ; Mon, 8 Jan 2018 14:27:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 63202223A0 for ; Mon, 8 Jan 2018 14:27:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 57C1428820; Mon, 8 Jan 2018 14:27:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 01013223A0 for ; Mon, 8 Jan 2018 14:27:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=z+2Th3j4fQAF3YtKPJ/V0E91/IzZGb/rQxaB5iyxcN4=; b=c5kRiW77cqDIjb Ms+Eu8Aujls1zBH18UAcEs3eGg267yMPzIXlafSlez54arx62DZD5wp5eW9L7x1Vhmn31pivhMR5n OepMNuzmqsmpot39djZdQolxczkatduKCU7IsNGUSSAaqwd2UyaCq+kHREmsxJXotmf+/gN9MfcFA C3GxX81Jy3SE8vHz/KdnukzSkAZvxDFSM/N+ehzc9mUAJivPc2tX9XwjPq2QVZbfaqq/1HCA1om1Y 6gNz6WsRj6efk6C7FWXJ8jtcfAUCIsqbWv3wpyDiq2spMFFzDjeciuXt5qxdhhDLHOV11gGhDyz/7 E7rSdRb4maL0z4pcSkFg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1eYYOO-0007Wh-6g; Mon, 08 Jan 2018 14:27:12 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1eYYOK-0007QE-P4 for linux-arm-kernel@lists.infradead.org; Mon, 08 Jan 2018 14:27:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1D8361529; Mon, 8 Jan 2018 06:26:56 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E27A03F318; Mon, 8 Jan 2018 06:26:55 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id CB5181AE3318; Mon, 8 Jan 2018 14:26:57 +0000 (GMT) Date: Mon, 8 Jan 2018 14:26:57 +0000 From: Will Deacon To: James Morse Subject: Re: [PATCH v2 07/11] arm64: Add skeleton to harden the branch predictor against aliasing attacks Message-ID: <20180108142657.GE25869@arm.com> References: <1515157961-20963-1-git-send-email-will.deacon@arm.com> <1515157961-20963-8-git-send-email-will.deacon@arm.com> <5A53611C.5030003@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <5A53611C.5030003@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180108_062708_890079_DF62CA00 X-CRM114-Status: GOOD ( 15.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lorenzo.pieralisi@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, labbott@redhat.com, christoffer.dall@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Hi James, Thanks for having a look. On Mon, Jan 08, 2018 at 12:16:28PM +0000, James Morse wrote: > On 05/01/18 13:12, Will Deacon wrote: > > diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c > > index 22168cd0dde7..5203b6040cb6 100644 > > --- a/arch/arm64/mm/fault.c > > +++ b/arch/arm64/mm/fault.c > > @@ -318,6 +318,7 @@ static void __do_user_fault(struct task_struct *tsk, unsigned long addr, > > lsb = PAGE_SHIFT; > > si.si_addr_lsb = lsb; > > > > + arm64_apply_bp_hardening(); > > Due to the this_cpu_ptr() call: > > | BUG: using smp_processor_id() in preemptible [00000000] code: print_my_pa/2093 > | caller is debug_smp_processor_id+0x1c/0x24 > | CPU: 0 PID: 2093 Comm: print_my_pa Tainted: G W > 4.15.0-rc3-00044-g7f0aaec94f27-dirty #8950 > | Call trace: > | dump_backtrace+0x0/0x164 > | show_stack+0x14/0x1c > | dump_stack+0xa4/0xdc > | check_preemption_disabled+0xfc/0x100 > | debug_smp_processor_id+0x1c/0x24 > | __do_user_fault+0xcc/0x180 > | do_page_fault+0x14c/0x364 > | do_translation_fault+0x40/0x48 > | do_mem_abort+0x40/0xb8 > | el0_da+0x20/0x24 Ah bugger, yes, we re-enabled interrupts in the entry code when we took the fault initially. > Make it a TIF flag? > > (Seen with arm64's kpti-base tag and this series) A TIF flag is still a bit fiddly, because we need to track that the predictor could be dirty on this CPU. Instead, I'll postpone the re-enabling of IRQs on el0_ia until we're in C code -- we can quickly a check on the address before doing that. See below. Will --->8 diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 80b539845da6..07a7d4db8ec4 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -721,12 +721,15 @@ el0_ia: * Instruction abort handling */ mrs x26, far_el1 - enable_daif + enable_da_f +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_off +#endif ct_user_exit mov x0, x26 mov x1, x25 mov x2, sp - bl do_mem_abort + bl do_el0_ia_bp_hardening b ret_to_user el0_fpsimd_acc: /* diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 5203b6040cb6..0e671ddf4855 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -318,7 +318,6 @@ static void __do_user_fault(struct task_struct *tsk, unsigned long addr, lsb = PAGE_SHIFT; si.si_addr_lsb = lsb; - arm64_apply_bp_hardening(); force_sig_info(sig, &si, tsk); } @@ -709,6 +708,23 @@ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, arm64_notify_die("", regs, &info, esr); } +asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, + unsigned int esr, + struct pt_regs *regs) +{ + /* + * We've taken an instruction abort from userspace and not yet + * re-enabled IRQs. If the address is a kernel address, apply + * BP hardening prior to enabling IRQs and pre-emption. + */ + if (addr > TASK_SIZE) + arm64_apply_bp_hardening(); + + local_irq_enable(); + do_mem_abort(addr, esr, regs); +} + + asmlinkage void __exception do_sp_pc_abort(unsigned long addr, unsigned int esr, struct pt_regs *regs)