From patchwork Fri Jan 19 23:17:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 10176101 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A6189602B1 for ; Fri, 19 Jan 2018 23:19:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 950BD287DE for ; Fri, 19 Jan 2018 23:19:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8960F287E2; Fri, 19 Jan 2018 23:19:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3DE42287DE for ; Fri, 19 Jan 2018 23:19:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=AiRzdzPpCXXXRFxRD6Iw+YZBIWZkJfmRDYWOCezlBs4=; b=Vv4MnjfWONliNVL5mXEqoqqIHZ qF3yRP19UUnmO7BxY05chl5455vzmLdIQusFwotyUujfyGmZXHIfhdLbC2f1nIBAqQKGUA9isyg3y Jw1Vxw1U7qqmsC4Yyg+GjmWhD1qKkRFB8oTi1A8vTm4eGWJIimdAdwDue86BS7YISLlEj4qTcR8o/ e87CQ4CF1rN10+M6CNu8UhLc6da8ej5Pz3u2VvF4qORhL4zT+uLgZS9yQ3bVDycxKMvpNdE9KR+hk 8R/dETBzYQfrqPxldfFson6lOy1gTUHs+Gq1vI56W1wOCkbxMHzPDsFejz6EXmBEsZJKuqj6HqVjq 8CMsSW0g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1ecfw6-00077w-4B; Fri, 19 Jan 2018 23:19:02 +0000 Received: from bisque.maple.relay.mailchannels.net ([23.83.214.18]) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1ecfvk-0006ep-HR for linux-arm-kernel@lists.infradead.org; Fri, 19 Jan 2018 23:18:42 +0000 X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id 87AB8120D37; Fri, 19 Jan 2018 23:18:27 +0000 (UTC) Received: from hermes.aosc.io (unknown [100.96.16.38]) (Authenticated sender: lmn-TZDUIOWCRQMW) by relay.mailchannels.net (Postfix) with ESMTPA id DCFAA1214C7; Fri, 19 Jan 2018 23:18:25 +0000 (UTC) X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from hermes.aosc.io (hermes.aosc.io [172.18.52.53]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384) by 0.0.0.0:2500 (trex/5.13.1); Fri, 19 Jan 2018 23:18:27 +0000 X-MC-Relay: Neutral X-MailChannels-SenderId: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io X-MailChannels-Auth-Id: lmn-TZDUIOWCRQMW X-Fumbling-Share: 6a6ed52203beec71_1516403907237_1981548165 X-MC-Loop-Signature: 1516403907237:718107311 X-MC-Ingress-Time: 1516403907237 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id EBF0B56068; Fri, 19 Jan 2018 23:18:18 +0000 (UTC) From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij Subject: [RFC PATCH 3/9] irqchip/sun4i: add support for suniv interrupt controller Date: Sat, 20 Jan 2018 07:17:29 +0800 Message-Id: <20180119231735.61504-4-icenowy@aosc.io> In-Reply-To: <20180119231735.61504-1-icenowy@aosc.io> References: <20180119231735.61504-1-icenowy@aosc.io> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The new F-series SoCs (suniv) from Allwinner use an stripped version of the interrupt controller in A10/A13. Add support for it in irq-sun4i driver. Signed-off-by: Icenowy Zheng --- drivers/irqchip/irq-sun4i.c | 43 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index e3e5b9132b75..64ae41379802 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -23,13 +23,26 @@ #include +enum sun4i_irq_type { + sun4i_ic, + suniv_ic +}; + +static enum sun4i_irq_type sun4i_irq_type; +static int sun4i_irq_enable_reg_offset; +static int sun4i_irq_mask_reg_offset; + #define SUN4I_IRQ_VECTOR_REG 0x00 #define SUN4I_IRQ_PROTECTION_REG 0x08 #define SUN4I_IRQ_NMI_CTRL_REG 0x0c #define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x) #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x) -#define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x) -#define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x) +#define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40 +#define SUN4I_IRQ_MASK_REG_OFFSET 0x50 +#define SUNIV_IRQ_ENABLE_REG_OFFSET 0x20 +#define SUNIV_IRQ_MASK_REG_OFFSET 0x30 +#define SUN4I_IRQ_ENABLE_REG(x) (sun4i_irq_enable_reg_offset + 0x4 * x) +#define SUN4I_IRQ_MASK_REG(x) (sun4i_irq_mask_reg_offset + 0x4 * x) static void __iomem *sun4i_irq_base; static struct irq_domain *sun4i_irq_domain; @@ -115,8 +128,9 @@ static int __init sun4i_of_init(struct device_node *node, writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1)); writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2)); - /* Enable protection mode */ - writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG); + /* Enable protection mode (not available in suniv) */ + if (sun4i_irq_type == sun4i_ic) + writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG); /* Configure the external interrupt source type */ writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG); @@ -130,7 +144,26 @@ static int __init sun4i_of_init(struct device_node *node, return 0; } -IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init); + +static int __init sun4i_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + sun4i_irq_type = sun4i_ic; + sun4i_irq_enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; + sun4i_irq_mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; + sun4i_of_init(node, parent); +} +IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init); + +static int __init suniv_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + sun4i_irq_type = suniv_ic; + sun4i_irq_enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET; + sun4i_irq_mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET; + sun4i_of_init(node, parent); +} +IRQCHIP_DECLARE(allwinner_suniv_ic, "allwinner,suniv-ic", suniv_ic_of_init); static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) {