From patchwork Fri Jan 26 01:13:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 10184969 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 468AE601D5 for ; Fri, 26 Jan 2018 01:14:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 373A4288BF for ; Fri, 26 Jan 2018 01:14:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2C11328BDD; Fri, 26 Jan 2018 01:14:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B73DA288BF for ; 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Fri, 26 Jan 2018 01:14:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516929242; bh=h/LJT6M4bm56SDPRG73MGlYMEBdwlhitHTVnaer5bT4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BEJqXa+6h6NVKHliC6AvGJyL4cNmeihCgNaLDRVAl6Yg/6rmTxgNtZO9vJpxzysOC uKsHyJLnVj0hlOoYpYVfzUP4Cw4p0ch2Tpq3suVwyMMXVLc5iWrhOoiVO7cWGTVn27 cEexuYMpq0aGbkAE7OsFfsMxY8WD5RaItY5bDn3s= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 547AD6032C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org From: Stephen Boyd To: Linus Walleij Subject: [PATCH v2 2/3] gpiolib-of: Support 'reserved-gpio-ranges' property Date: Thu, 25 Jan 2018 17:13:59 -0800 Message-Id: <20180126011400.2191-3-sboyd@codeaurora.org> X-Mailer: git-send-email 2.15.0.374.g5f9953d2c365 In-Reply-To: <20180126011400.2191-1-sboyd@codeaurora.org> References: <20180126011400.2191-1-sboyd@codeaurora.org> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Timur Tabi , linux-kernel@vger.kernel.org, Bjorn Andersson , Grant Likely , linux-gpio@vger.kernel.org, Andy Shevchenko , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues. Add support for a DT property to describe the set of GPIOs that are available for use so that higher level OSes are able to know what pins to avoid reading/writing. For now, we plumb this into the gpiochip irq APIs so that GPIO/pinctrl drivers can use the gpiochip_irqchip_irq_valid() to test validity of GPIOs. Signed-off-by: Stephen Boyd --- Or this can move into a dedicated API and not be tied to the irq code. Something like of_gpiochip_init_valid_mask? drivers/gpio/gpiolib-of.c | 28 ++++++++++++++++++++++++++++ drivers/gpio/gpiolib.c | 9 +++++++++ 2 files changed, 37 insertions(+) diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index 564bb7a31da4..194b3306ef74 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -498,6 +498,32 @@ void of_mm_gpiochip_remove(struct of_mm_gpio_chip *mm_gc) } EXPORT_SYMBOL(of_mm_gpiochip_remove); +#ifdef CONFIG_GPIOLIB_IRQCHIP +static void of_gpiochip_init_irq_valid_mask(struct gpio_chip *chip) +{ + int len, i; + u32 start, count; + struct device_node *np = chip->of_node; + + len = of_property_count_u32_elems(np, "reserved-gpio-ranges"); + if (len < 0 || len % 2 != 0) + return; + + for (i = 0; i < len; i += 2) { + of_property_read_u32_index(np, "reserved-gpio-ranges", + i, &start); + of_property_read_u32_index(np, "reserved-gpio-ranges", + i + 1, &count); + if (start >= chip->ngpio || start + count >= chip->ngpio) + continue; + + bitmap_clear(chip->irq.valid_mask, start, count); + } +}; +#else +static void of_gpiochip_init_irq_valid_mask(struct gpio_chip *chip) { } +#endif + #ifdef CONFIG_PINCTRL static int of_gpiochip_add_pin_range(struct gpio_chip *chip) { @@ -602,6 +628,8 @@ int of_gpiochip_add(struct gpio_chip *chip) if (chip->of_gpio_n_cells > MAX_PHANDLE_ARGS) return -EINVAL; + of_gpiochip_init_irq_valid_mask(chip); + status = of_gpiochip_add_pin_range(chip); if (status) return status; diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 930676ec9847..8483850463e6 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1483,6 +1483,15 @@ static struct gpio_chip *find_chip_by_name(const char *name) static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip) { +#ifdef CONFIG_OF_GPIO + int size; + struct device_node *np = gpiochip->of_node; + + size = of_property_count_u32_elems(np, "reserved-gpio-ranges"); + if (size > 0 && size % 2 == 0) + gpiochip->irq.need_valid_mask = true; +#endif + if (!gpiochip->irq.need_valid_mask) return 0;