From patchwork Thu Feb 15 21:03:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 10223679 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CD83B602CB for ; Thu, 15 Feb 2018 21:22:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC57D2953B for ; Thu, 15 Feb 2018 21:22:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B07A62953F; Thu, 15 Feb 2018 21:22:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2B3502953B for ; Thu, 15 Feb 2018 21:22:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Ki1becdYIFCiMPHI69bENClDxFbGQOoalPVQd5msbHA=; b=SfX686Lbxcl76UFMOGG5Ajtnhm xaPMkONgkOF8cKSHCVMQUDYQYkCBOYRVpaF+G5hnGYPOAOEOwAeUEv8M6lofs+FPI0fA5J9D8gVYl f/hYjI3Vquc+jy0Ysk9yg1/BanZaW4I/Zb+0rs3fkdMTRWQ/3JnlAb+GWQ+AP4QR29YvGD7i8disv 7BwkkVeRUww5fsdDzaDPfiJLZJ9qvjeGMHCtdr3zH88tFNNtIa35R8IkvDEiAlqPj2QXuO9h0n8Wo Bb3PxYws6uS/S3nrqq5jvW753KZtLniF5Y/JSCGDnRt5c+Ho75IkXJZHvwWnPQbqF/2UYWbiXU1Tz tz1hFJ/w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1emQyp-00081X-0r; Thu, 15 Feb 2018 21:22:11 +0000 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1emQhf-0000NJ-N0 for linux-arm-kernel@lists.infradead.org; Thu, 15 Feb 2018 21:05:14 +0000 Received: by mail-wm0-x243.google.com with SMTP id h74so3268021wme.5 for ; Thu, 15 Feb 2018 13:04:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dSHKIy49GPJ2N8Zsct45xva1Va+BGafr4ueAQGvRipE=; b=L2nCtICAsd6VYHoht7zK4wX1jJhrs1i3cc6/rYogDs3ZzxasRszaEQ0Uj8Gik4t72C lCibFye7A774NWODkdTazgUf01XipGwyq7lwzP/yF2eJI81HgGQbsio1MSwUoebGiDt7 9vNvr2oA50KykBfGQhKgn+wO2M0QHNA+s1Exw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dSHKIy49GPJ2N8Zsct45xva1Va+BGafr4ueAQGvRipE=; b=EaDnMJTOmv9NmYuyvAmcwb4C2xLf7g5XYmDm/8dVRvHgvxjUuZMMxWsLr4CZM+aSkK wytmBquz10F9nrAEv+VgiGtTh3K58/W/T2aqF+Xd0mmdPFa9rVjEDGxrkVNJk4tnJiMz AQz6YmCD2xl/7GEYX/udi4e8kilJY0BlZJHjKSZNFIzaCd1llnEphhElzoNpmKA9/c5w atwEHD1fD0Khefm+0v5nPdEWRhqL6Qo+XFVKbBwU/cjhFfEVWftMVFAOTBPJlQpj3Nu6 Ux8HUphlD6WbL6t/yaBYcOZYWPa0/s7YNMzPG/ERi751kHIX+HJTC1+pNJ29aTPYmmNG PVUw== X-Gm-Message-State: APf1xPCWSXmqcx3R1J2UVYVHW9zqFuwIcam6VOLV9LY3O1AuO5Ceoto4 XjS21oa2BKQVgqInA5f8p+xRVQ== X-Google-Smtp-Source: AH8x224mMapAhLALF6iwDBdQalhqw0QiCz3HvYon7LDIRQhZJRUuB8856v5mQv4zsNgjpKyd1XYtdQ== X-Received: by 10.80.230.148 with SMTP id z20mr5176127edm.61.1518728665958; Thu, 15 Feb 2018 13:04:25 -0800 (PST) Received: from localhost.localdomain (x50d2404e.cust.hiper.dk. [80.210.64.78]) by smtp.gmail.com with ESMTPSA id p55sm8220030edc.15.2018.02.15.13.04.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Feb 2018 13:04:24 -0800 (PST) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 25/40] KVM: arm64: Introduce framework for accessing deferred sysregs Date: Thu, 15 Feb 2018 22:03:17 +0100 Message-Id: <20180215210332.8648-26-christoffer.dall@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20180215210332.8648-1-christoffer.dall@linaro.org> References: <20180215210332.8648-1-christoffer.dall@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180215_130427_966436_B846E43B X-CRM114-Status: GOOD ( 18.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , kvm@vger.kernel.org, Marc Zyngier , Tomasz Nowicki , Julien Grall , Yury Norov , Christoffer Dall , Dave Martin , Shih-Wei Li MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We are about to defer saving and restoring some groups of system registers to vcpu_put and vcpu_load on supported systems. This means that we need some infrastructure to access system registes which supports either accessing the memory backing of the register or directly accessing the system registers, depending on the state of the system when we access the register. We do this by defining read/write accessor functions, which can handle both "immediate" and "deferrable" system registers. Immediate registers are always saved/restored in the world-switch path, but deferrable registers are only saved/restored in vcpu_put/vcpu_load when supported and sysregs_loaded_on_cpu will be set in that case. Note that we don't use the deferred mechanism yet in this patch, but only introduce infrastructure. This is to improve convenience of review in the subsequent patches where it is clear which registers become deferred. Signed-off-by: Christoffer Dall Reviewed-by: Marc Zyngier Reviewed-by: Andrew Jones --- Notes: Changes since v3: - Changed to a switch-statement based approach to improve readability. Changes since v2: - New patch (deferred register handling has been reworked) arch/arm64/include/asm/kvm_host.h | 8 ++++++-- arch/arm64/kvm/sys_regs.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 68398bf7882f..b463b5e28959 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -284,6 +284,10 @@ struct kvm_vcpu_arch { /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ u64 vsesr_el2; + + /* True when deferrable sysregs are loaded on the physical CPU, + * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */ + bool sysregs_loaded_on_cpu; }; #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) @@ -296,8 +300,8 @@ struct kvm_vcpu_arch { */ #define __vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) -#define vcpu_read_sys_reg(v,r) __vcpu_sys_reg(v,r) -#define vcpu_write_sys_reg(v,r,n) do { __vcpu_sys_reg(v,r) = n; } while (0) +u64 vcpu_read_sys_reg(struct kvm_vcpu *vcpu, int reg); +void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, int reg, u64 val); /* * CP14 and CP15 live in the same array, as they are backed by the diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a05d2c01c786..b3c3f014aa61 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -76,6 +77,38 @@ static bool write_to_read_only(struct kvm_vcpu *vcpu, return false; } +u64 vcpu_read_sys_reg(struct kvm_vcpu *vcpu, int reg) +{ + if (!vcpu->arch.sysregs_loaded_on_cpu) + goto immediate_read; + + /* + * All system registers listed in the switch are not saved on every + * exit from the guest but are only saved on vcpu_put. + */ + switch (reg) { + } + +immediate_read: + return __vcpu_sys_reg(vcpu, reg); +} + +void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, int reg, u64 val) +{ + if (!vcpu->arch.sysregs_loaded_on_cpu) + goto immediate_write; + + /* + * All system registers listed in the switch are not restored on every + * entry to the guest but are only restored on vcpu_load. + */ + switch (reg) { + } + +immediate_write: + __vcpu_sys_reg(vcpu, reg) = val; +} + /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ static u32 cache_levels;