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h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=c+KYNG5BmwW8H1sCmQ8Pi7+XQ3jKtU28QBmicWKzER0=; b=FMcgFzYgg8WclOnuqxQq+SeBwkebVt/dd5GBxYpdiYtVXyZ9qkGcSRdh4+kmLRsfZG +7SCyKZGxYiCdkHUuK1ET/s7ivjfGEw4Z5xJSMsFNpyzcKlcY/MA2rPTos0aH3kh1R7j X0VuqecYDY5qF7v3VriXGOoyltFH3fIAiRLZA0O5r3rsoPK5qTr/3F528xzxpgwJnjZH C/4ex69aCHaOJWgcBOMQRuyY9N3wjDWm7UHoLv3q02VL18onjC2bQbC9Ckm3GHturLG4 WxpZGicKZ6v57CI3Bb4PF75Wr2MZlV0ILuq6+BCukA+eGr/Mg+DR2lG+W5ItvNfWcFUt JyxQ== X-Gm-Message-State: APf1xPApWuS+Pa5kD/MX6XC3CjxmCouEBp9kwngqSmGv5LwcbDr6e4cf PqIdk7U6WxSLUy34JBC/GBwOAA== X-Google-Smtp-Source: AG47ELv0kkRcIvndZxRCia0nLWLms+XJAy6BPAenTpIOoBCa3Vh2kmONpHI++3mfA7i98fEa9/pZFg== X-Received: by 10.99.56.11 with SMTP id f11mr19738261pga.63.1520467061248; Wed, 07 Mar 2018 15:57:41 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id b4sm35682968pfa.3.2018.03.07.15.57.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Mar 2018 15:57:40 -0800 (PST) Subject: [PATCH v3 2/5] RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler Date: Wed, 7 Mar 2018 15:57:28 -0800 Message-Id: <20180307235731.22627-3-palmer@sifive.com> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307235731.22627-1-palmer@sifive.com> References: <20180307235731.22627-1-palmer@sifive.com> From: Palmer Dabbelt To: linux@armlinux.org.uk, catalin.marinas@arm.com, Will Deacon , jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openrisc@lists.librecores.org, linux-riscv@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180307_155752_331484_37D2347F X-CRM114-Status: GOOD ( 18.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The old mechanism for handling IRQs on RISC-V was pretty ugly: the arch code looked at the Kconfig entry for our first-level irqchip driver and called into it directly. This patch uses the new generic IRQ handling infastructure, which essentially just deletes a bunch of code. This does add an additional load to the interrupt latency, but there's a lot of tuning left to be done there on RISC-V so I think it's OK for now. Reviewed-by: Christoph Hellwig Acked-by: Stafford Horne Signed-off-by: Palmer Dabbelt --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/Kbuild | 1 + arch/riscv/kernel/entry.S | 7 +++---- arch/riscv/kernel/irq.c | 13 ------------- 4 files changed, 5 insertions(+), 17 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 04807c7f64cc..148865de1692 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -33,6 +33,7 @@ config RISCV select MODULES_USE_ELF_RELA if MODULES select THREAD_INFO_IN_TASK select RISCV_TIMER + select GENERIC_IRQ_MULTI_HANDLER config MMU def_bool y diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild index 4286a5f83876..1e5fd280fb4d 100644 --- a/arch/riscv/include/asm/Kbuild +++ b/arch/riscv/include/asm/Kbuild @@ -15,6 +15,7 @@ generic-y += fcntl.h generic-y += futex.h generic-y += hardirq.h generic-y += hash.h +generic-y += handle_irq.h generic-y += hw_irq.h generic-y += ioctl.h generic-y += ioctls.h diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 56fa592cfa34..9aaf6c986771 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -167,10 +167,9 @@ ENTRY(handle_exception) bge s4, zero, 1f /* Handle interrupts */ - slli a0, s4, 1 - srli a0, a0, 1 - move a1, sp /* pt_regs */ - tail do_IRQ + move a0, sp /* pt_regs */ + REG_L a1, handle_arch_irq + jr a1 1: /* Exceptions run with interrupts enabled */ csrs sstatus, SR_SIE diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 328718e8026e..b74cbfbce2d0 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -24,16 +24,3 @@ void __init init_IRQ(void) { irqchip_init(); } - -asmlinkage void __irq_entry do_IRQ(unsigned int cause, struct pt_regs *regs) -{ -#ifdef CONFIG_RISCV_INTC - /* - * FIXME: We don't want a direct call to riscv_intc_irq here. The plan - * is to put an IRQ domain here and let the interrupt controller - * register with that, but I poked around the arm64 code a bit and - * there might be a better way to do it (ie, something fully generic). - */ - riscv_intc_irq(cause, regs); -#endif -}