From patchwork Fri Mar 16 14:02:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 10287379 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7EF3B602C2 for ; Fri, 16 Mar 2018 14:06:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6E86228EE0 for ; Fri, 16 Mar 2018 14:06:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5F0D928EE2; Fri, 16 Mar 2018 14:06:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3F1FB28EE0 for ; Fri, 16 Mar 2018 14:06:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=W6QtgGaFad6NXGir5DhawX188s/wChQPknjYsZw3N7c=; b=U7pFAkCw3/zCnYH9omLEt+tEND KbJQiGTJdoQxiMIsWp4kVEfZt53+EBFe39bIyqVC5M7dLPtaAPUKcvjyyNattFFmPihSKrwFkzjIA Ji0IhiXwE764LUg7RLmkR1gxWJagotWo350LJckaGJ4vLovz6bCYKvOmABLTWX49NaViGEs7M0TRo AJ0EfKgPig8p5RDAKVKHgbFbJbukWRH4TIy0LvpFmAHoCRCXzjwai0O2KOOxYjUZA3YQYHEmhfvnS pxNGD9jFBuE5edIxtIErbvAnTlFQhrj915gFeNk9PsBULqu1jileMOc4DUcwd+sLFOE8gWi1YNQ6H B+c6BPgg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1ewq07-0003I9-L9; Fri, 16 Mar 2018 14:06:31 +0000 Received: from giant.birch.relay.mailchannels.net ([23.83.209.68]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1ewpxx-00019Z-D8 for linux-arm-kernel@lists.infradead.org; Fri, 16 Mar 2018 14:04:24 +0000 X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id 4C02D5C0239; Fri, 16 Mar 2018 14:04:06 +0000 (UTC) Received: from hermes.aosc.io (unknown [100.96.18.70]) (Authenticated sender: lmn-TZDUIOWCRQMW) by relay.mailchannels.net (Postfix) with ESMTPA id 5FD4E5C0F60; Fri, 16 Mar 2018 14:04:05 +0000 (UTC) X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from hermes.aosc.io (hermes.aosc.io [172.18.49.137]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384) by 0.0.0.0:2500 (trex/5.14.1); Fri, 16 Mar 2018 14:04:06 +0000 X-MC-Relay: Neutral X-MailChannels-SenderId: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io X-MailChannels-Auth-Id: lmn-TZDUIOWCRQMW X-Trade-Trail: 1a6483123b9fad03_1521209046102_338768346 X-MC-Loop-Signature: 1521209046102:3747313357 X-MC-Ingress-Time: 1521209046101 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id C647D59788; Fri, 16 Mar 2018 14:04:00 +0000 (UTC) From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Linus Walleij Subject: [PATCH v4 3/9] pinctrl: sunxi: change irq_bank_base to irq_bank_map Date: Fri, 16 Mar 2018 22:02:09 +0800 Message-Id: <20180316140215.28663-4-icenowy@aosc.io> In-Reply-To: <20180316140215.28663-1-icenowy@aosc.io> References: <20180316140215.28663-1-icenowy@aosc.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180316_070418_370773_90949CE2 X-CRM114-Status: GOOD ( 15.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard --- Extracted in v4. drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 4 +++- drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 4 +++- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 7 +++++-- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c index da387211a75e..f043afa1aac5 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c @@ -481,11 +481,13 @@ static const struct sunxi_desc_pin sun8i_a33_pins[] = { SUNXI_FUNCTION(0x3, "uart3")), /* CTS */ }; +static const unsigned int sun8i_a33_pinctrl_irq_bank_map[] = { 1, 2 }; + static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = { .pins = sun8i_a33_pins, .npins = ARRAY_SIZE(sun8i_a33_pins), .irq_banks = 2, - .irq_bank_base = 1, + .irq_bank_map = sun8i_a33_pinctrl_irq_bank_map, .disable_strict_mode = true, }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c index 496ba34e1f5f..6704ce8e5e3d 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c @@ -293,11 +293,13 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = { SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ }; +static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 }; + static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = { .pins = sun8i_v3s_pins, .npins = ARRAY_SIZE(sun8i_v3s_pins), .irq_banks = 2, - .irq_bank_base = 1, + .irq_bank_map = sun8i_v3s_pinctrl_irq_bank_map, .irq_read_needs_mux = true }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 466840d886f6..4a892e7dde66 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -110,7 +110,7 @@ struct sunxi_pinctrl_desc { int npins; unsigned pin_base; unsigned irq_banks; - unsigned irq_bank_base; + const unsigned int *irq_bank_map; bool irq_read_needs_mux; bool disable_strict_mode; }; @@ -265,7 +265,10 @@ static inline u32 sunxi_pull_offset(u16 pin) static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank) { - return desc->irq_bank_base + bank; + if (!desc->irq_bank_map) + return bank; + else + return desc->irq_bank_map[bank]; } static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,