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[86.26.100.93]) by smtp.gmail.com with ESMTPSA id n7sm1322187wrg.20.2018.03.20.02.31.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 20 Mar 2018 02:31:04 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: andy.gross@linaro.org, linux-arm-msm@vger.kernel.org Subject: [PATCH] ARM: dts: db600c: add support to pcie refclk Date: Tue, 20 Mar 2018 09:28:40 +0000 Message-Id: <20180320092840.4600-1-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.16.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180320_023117_210754_1D3B654F X-CRM114-Status: GOOD ( 12.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, david.brown@linaro.org, robh+dt@kernel.org, Srinivas Kandagatla , linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla This patch adds support to external pcie refclk. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-db600c.dts | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-db600c.dts index 50151ef6e912..7587088c122f 100644 --- a/arch/arm/boot/dts/qcom-apq8064-db600c.dts +++ b/arch/arm/boot/dts/qcom-apq8064-db600c.dts @@ -45,6 +45,18 @@ }; + clocks { + compatible = "simple-bus"; + pcie_refclk: pcie-refclk { + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + compatible = "gpio-gate-clock"; + clocks = <&rpmcc 27>; + #clock-cells = <0>; + enable-gpios = <&pm8921_gpio 22 GPIO_ACTIVE_HIGH>; + }; + }; + hdmi-out { compatible = "hdmi-connector"; type = "a"; @@ -140,6 +152,16 @@ qcom,ssbi@500000 { pmic@0 { + gpio@150 { + pcie_pins: pcie_pins { + pios { + pins = "gpio22"; + function = "normal"; + power-source = ; + }; + }; + }; + mpps@50 { pcie_perst: pcie-perst { pinconf { @@ -439,6 +461,11 @@ pinctrl-0 = <&pcie_perst>; pinctrl-names = "default"; perst-gpio = <&pm8921_mpps 1 GPIO_ACTIVE_LOW>; + clocks = <&gcc PCIE_A_CLK>, + <&gcc PCIE_H_CLK>, + <&gcc PCIE_PHY_REF_CLK>, + <&pcie_refclk>; + clock-names = "core", "iface", "phy", "ref"; }; /* OTG */