From patchwork Fri Mar 30 07:22:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Suloev X-Patchwork-Id: 10317235 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 673FA602A7 for ; Fri, 30 Mar 2018 07:26:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D4032A54E for ; Fri, 30 Mar 2018 07:26:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 41F772A55B; Fri, 30 Mar 2018 07:26:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A059B2A54E for ; Fri, 30 Mar 2018 07:26:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=3srfc5ghIBB+VL9b6NjeOFwJR1Xl2WE0gdtD7e5ZaVU=; b=OeevX7Qj9DhdweRvMzVV2DBXVu vSOZQZ+gnyhTgs3Sw7pa79V5NAEXrb/L8L3h2Xj3PuDXGDZERqqGNJL/UUKi9X6dqzmda5hSXRRL+ nMl3g2tv9RBBgElcnFASCH955fiSmOx/JsBNWC/1wr26rRY7ecqo0Y6YW7uXyGeJY6tse9Tc+9ahB 2voS5XaLOYV8ai4etmla6yGQRb/pjbQmSIMSWXq+Uqs0zWJWuH1IBcAtP2eCSQrGLksoN+Zbxxsvn aTdAb+HXFLB/AcjLfch8nAV7o/3T2fYMXMp5vMz/9v7p8ni5bZr7QQv+aeo1o/p6rv1rQeagmpNn0 kwuPA99A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f1oQk-0001qQ-9U; Fri, 30 Mar 2018 07:26:34 +0000 Received: from smtp57.i.mail.ru ([217.69.128.37]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1f1oNM-0006tW-FZ for linux-arm-kernel@lists.infradead.org; Fri, 30 Mar 2018 07:23:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=orpaltech.com; s=mailru; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=/ZkAp67hKLeYbaYot2SKoy+sjBA6vJ0hIaCen0qrVrI=; b=mQfwN5fX3rNFCYK96nsNrHka7G658mahb+cwnPTn0zD4qB59nDYE5LnwvvQFL2ppb9rZypGlCAL9tRw35mR/w8ee+cXcRwHialaIh3MiS57ZbRxFAgOmtTPH0H9d7flQ56DinHEdozw4Y86VbWWW4bPIT+i5R5d96qa8mJ3hOoI=; Received: by smtp57.i.mail.ru with esmtpa (envelope-from ) id 1f1oNB-0001IV-IU; Fri, 30 Mar 2018 10:22:54 +0300 From: Sergey Suloev To: Mark Brown , Maxime Ripard , Chen-Yu Tsai Subject: [PATCH 1/6] spi: sun6i: coding style/readability improvements Date: Fri, 30 Mar 2018 10:22:38 +0300 Message-Id: <20180330072243.19368-2-ssuloev@orpaltech.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180330072243.19368-1-ssuloev@orpaltech.com> References: <20180330072243.19368-1-ssuloev@orpaltech.com> Authentication-Results: smtp57.i.mail.ru; auth=pass smtp.auth=ssuloev@orpaltech.com smtp.mailfrom=ssuloev@orpaltech.com X-7FA49CB5: 0D63561A33F958A538E9FD8347209FA6BC0A8B6031D50A009C7BED3C7C76799E725E5C173C3A84C39D7D3120FB43BDE306A40A42B1AF00E11D6A3D1828C120DEC4224003CC836476C0CAF46E325F83A50BF2EBBBDD9D6B0F05F538519369F3743B503F486389A921A5CC5B56E945C8DA X-Mailru-Sender: C5364AD02485212F3ACDC11E67D84917FB9ED6DAE09EA82C4E9ABD469779872F069BFC61DABEEB110841D3AAAB1726C63DDE9B364B0DF289264D2CD8C2503E8C22A194DADEED8EEDCA01A23BA9CD1BE7ED14614B50AE0675 X-Mras: OK X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180330_002304_756592_470C174E X-CRM114-Status: GOOD ( 12.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sergey Suloev , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Minor changes to fulfill the coding style and improve the readability. Signed-off-by: Sergey Suloev --- drivers/spi/spi-sun6i.c | 115 +++++++++++++++++++++++++++--------------------- 1 file changed, 65 insertions(+), 50 deletions(-) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index 8533f4e..ff790dc 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -88,8 +88,12 @@ #define SUN6I_TXDATA_REG 0x200 #define SUN6I_RXDATA_REG 0x300 +#define SUN6I_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST) + +#define SUN6I_SPI_MAX_SPEED_HZ 100000000 +#define SUN6I_SPI_MIN_SPEED_HZ 3000 + struct sun6i_spi { - struct spi_master *master; void __iomem *base_addr; struct clk *hclk; struct clk *mclk; @@ -189,6 +193,9 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) else reg &= ~SUN6I_TFR_CTL_CS_LEVEL; + /* We want to control the chip select manually */ + reg |= SUN6I_TFR_CTL_CS_MANUAL; + sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); } @@ -197,6 +204,48 @@ static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) return SUN6I_MAX_XFER_SIZE - 1; } +static int sun6i_spi_prepare_message(struct spi_master *master, + struct spi_message *msg) +{ + struct spi_device *spi = msg->spi; + struct sun6i_spi *sspi = spi_master_get_devdata(master); + u32 reg; + + /* + * Setup the transfer control register: Chip Select, + * polarities, etc. + */ + reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); + + if (spi->mode & SPI_CPOL) + reg |= SUN6I_TFR_CTL_CPOL; + else + reg &= ~SUN6I_TFR_CTL_CPOL; + + if (spi->mode & SPI_CPHA) + reg |= SUN6I_TFR_CTL_CPHA; + else + reg &= ~SUN6I_TFR_CTL_CPHA; + + if (spi->mode & SPI_LSB_FIRST) + reg |= SUN6I_TFR_CTL_FBS; + else + reg &= ~SUN6I_TFR_CTL_FBS; + + /* + * If it's a TX only transfer, we don't want to fill the RX + * FIFO with bogus data + */ + if (sspi->rx_buf) + reg &= ~SUN6I_TFR_CTL_DHB; + else + reg |= SUN6I_TFR_CTL_DHB; + + sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); + + return 0; +} + static int sun6i_spi_transfer_one(struct spi_master *master, struct spi_device *spi, struct spi_transfer *tfr) @@ -235,40 +284,6 @@ static int sun6i_spi_transfer_one(struct spi_master *master, (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) | (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS)); - /* - * Setup the transfer control register: Chip Select, - * polarities, etc. - */ - reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); - - if (spi->mode & SPI_CPOL) - reg |= SUN6I_TFR_CTL_CPOL; - else - reg &= ~SUN6I_TFR_CTL_CPOL; - - if (spi->mode & SPI_CPHA) - reg |= SUN6I_TFR_CTL_CPHA; - else - reg &= ~SUN6I_TFR_CTL_CPHA; - - if (spi->mode & SPI_LSB_FIRST) - reg |= SUN6I_TFR_CTL_FBS; - else - reg &= ~SUN6I_TFR_CTL_FBS; - - /* - * If it's a TX only transfer, we don't want to fill the RX - * FIFO with bogus data - */ - if (sspi->rx_buf) - reg &= ~SUN6I_TFR_CTL_DHB; - else - reg |= SUN6I_TFR_CTL_DHB; - - /* We want to control the chip select manually */ - reg |= SUN6I_TFR_CTL_CS_MANUAL; - - sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); /* Ensure that we have a parent clock fast enough */ mclk_rate = clk_get_rate(sspi->mclk); @@ -442,12 +457,24 @@ static int sun6i_spi_probe(struct platform_device *pdev) struct resource *res; int ret = 0, irq; - master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); + master = spi_alloc_master(&pdev->dev, sizeof(*sspi)); if (!master) { dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); return -ENOMEM; } + master->max_speed_hz = SUN6I_SPI_MAX_SPEED_HZ; + master->min_speed_hz = SUN6I_SPI_MIN_SPEED_HZ; + master->num_chipselect = 4; + master->mode_bits = SUN6I_SPI_MODE_BITS; + master->bits_per_word_mask = SPI_BPW_MASK(8); + master->set_cs = sun6i_spi_set_cs; + master->prepare_message = sun6i_spi_prepare_message; + master->transfer_one = sun6i_spi_transfer_one; + master->max_transfer_size = sun6i_spi_max_transfer_size; + master->dev.of_node = pdev->dev.of_node; + master->auto_runtime_pm = true; + platform_set_drvdata(pdev, master); sspi = spi_master_get_devdata(master); @@ -466,26 +493,14 @@ static int sun6i_spi_probe(struct platform_device *pdev) } ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, - 0, "sun6i-spi", sspi); + 0, dev_name(&pdev->dev), sspi); if (ret) { dev_err(&pdev->dev, "Cannot request IRQ\n"); goto err_free_master; } - sspi->master = master; sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); - master->max_speed_hz = 100 * 1000 * 1000; - master->min_speed_hz = 3 * 1000; - master->set_cs = sun6i_spi_set_cs; - master->transfer_one = sun6i_spi_transfer_one; - master->num_chipselect = 4; - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; - master->bits_per_word_mask = SPI_BPW_MASK(8); - master->dev.of_node = pdev->dev.of_node; - master->auto_runtime_pm = true; - master->max_transfer_size = sun6i_spi_max_transfer_size; - sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); if (IS_ERR(sspi->hclk)) { dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); @@ -525,7 +540,7 @@ static int sun6i_spi_probe(struct platform_device *pdev) ret = devm_spi_register_master(&pdev->dev, master); if (ret) { - dev_err(&pdev->dev, "cannot register SPI master\n"); + dev_err(&pdev->dev, "Couldn't register SPI master\n"); goto err_pm_disable; }