From patchwork Fri Mar 30 12:50:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Suloev X-Patchwork-Id: 10317799 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 70C136055B for ; Fri, 30 Mar 2018 14:39:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5E1A92A50E for ; Fri, 30 Mar 2018 14:39:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4FE692A597; Fri, 30 Mar 2018 14:39:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id ACAC52A50E for ; Fri, 30 Mar 2018 14:39:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=VF1VQaq4h2RoBzuO8PHLkrGcVaqwaN+NeytpyMa0pR8=; b=c0oDyE1LSldxYls4Bt8Vb4g6JL YzXJQNRdGJPXASLoNPir9DX3WyJJoz3kgeNUha/qrY1uxNxn45oOgSFg9pULkkv7dRPJEDqQic8lR EJafDSaZKBjqFsP30u6uGmWgCEKTQh+JCD/HzpBkLyx2s3Mg+8FTTa/nmJgWxDQHi+XH+deHFtEJQ a1TsyRtrloJhKTrEo1tW4znWjnSiZZPXrSR8MpoqFip98i3n2hytQb1p6cpod05ZD7YaTDfmaSpPO 6zY57v3z88iuGSobssx5ItQeaEuCIwAv29JqPIXOycYSojnWuIAhK0HDwYSSyIyuTdIEQR9OUjs89 8JMr5sug==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f1vBc-0001nv-5M; Fri, 30 Mar 2018 14:39:24 +0000 Received: from casper.infradead.org ([85.118.1.10]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1f1tW6-0005VS-09 for linux-arm-kernel@bombadil.infradead.org; Fri, 30 Mar 2018 12:52:26 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=zmQ9ZS0cQ8DDdlmRZUz6Petxb6GI3oQz6KjcQFrMRpg=; b=UlAFRc4KkaQ8hu0SVRG40ODpU 7iGn5lyMfT4FD/fFHl5dctPv+dKSC7ZLDB8c0440Q3fBXLiitrRnx4rTKiDgMbXAPDxsXWYltN6H8 nTS3eIkqmY4qCCknUl3bzoixLLeGYtyPNzUL5RlA0Y9Z74zxrG9UgEu+tu2jvXjMEnGOXalcpBOXJ W53c+iW7DgrDmiQPV1FWiEz58xofFFU3CgjvhmLKZtPpsi4dP7fqnk7Fqy9BMhmGQsxcBjimefDrN KdIJ0RLHmUDbx/GN1Z1QQYqKsrnpxv1CqDci+WYFPjLFRWOj0m0VJDkJHIGU03Be2LCd/QvitKIXS 2n/M4+ikg==; Received: from smtp58.i.mail.ru ([217.69.128.38]) by casper.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1f1tUt-0008VS-00 for linux-arm-kernel@lists.infradead.org; Fri, 30 Mar 2018 12:51:12 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=orpaltech.com; s=mailru; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=zmQ9ZS0cQ8DDdlmRZUz6Petxb6GI3oQz6KjcQFrMRpg=; b=V1IFOvPlExwCVFFAdMVkkIqwaxJ+1I1qUHwz4juHc1Sb2AmgAIDicUA05XRjha9UtOS06X+M0kq6DsxvTczbMXiLORW5YtHCzlhB5flM+GJtph3oOCU/LAXVrYI2aXREi7Io6Nq52pLQpzpkIIzhTlU9H3B3a6ZlGDnYe8p2//w=; Received: by smtp58.i.mail.ru with esmtpa (envelope-from ) id 1f1tUc-0001cV-TZ; Fri, 30 Mar 2018 15:50:55 +0300 From: Sergey Suloev To: Mark Brown , Maxime Ripard , Chen-Yu Tsai Subject: [PATCH v2 1/6] spi: sun6i: coding style/readability improvements Date: Fri, 30 Mar 2018 15:50:42 +0300 Message-Id: <20180330125047.13936-2-ssuloev@orpaltech.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180330125047.13936-1-ssuloev@orpaltech.com> References: <20180330125047.13936-1-ssuloev@orpaltech.com> Authentication-Results: smtp58.i.mail.ru; auth=pass smtp.auth=ssuloev@orpaltech.com smtp.mailfrom=ssuloev@orpaltech.com X-7FA49CB5: 0D63561A33F958A5E38A14485A1D41EB26FD46E76099F7CD1C50E35CC54CC232725E5C173C3A84C3EBF4D8D28E8B6903ED2F9B9BFAFF19550555CCFDA08FA3FAC4224003CC836476C0CAF46E325F83A50BF2EBBBDD9D6B0F5D41B9178041F3E72623479134186CDE6BA297DBC24807EABDAD6C7F3747799A X-Mailru-Sender: C5364AD02485212F3ACDC11E67D84917C63AC967F29A4BB76A903DEFD0FF3972069BFC61DABEEB110841D3AAAB1726C63DDE9B364B0DF289264D2CD8C2503E8C22A194DADEED8EEDCA01A23BA9CD1BE7ED14614B50AE0675 X-Mras: OK X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180330_135111_095012_3FFBA9F9 X-CRM114-Status: GOOD ( 17.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sergey Suloev , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Minor changes to fulfill the coding style and improve the readability of the code. Changes in v2: 1) Fixed issue with misplacing a piece of code that requires access to the transfer structure into sun6i_spi_prepare_message() function where the transfer structure is not available. Signed-off-by: Sergey Suloev --- drivers/spi/spi-sun6i.c | 97 +++++++++++++++++++++++++++++-------------------- 1 file changed, 58 insertions(+), 39 deletions(-) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index 8533f4e..88ad45e 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -88,8 +88,12 @@ #define SUN6I_TXDATA_REG 0x200 #define SUN6I_RXDATA_REG 0x300 +#define SUN6I_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST) + +#define SUN6I_SPI_MAX_SPEED_HZ 100000000 +#define SUN6I_SPI_MIN_SPEED_HZ 3000 + struct sun6i_spi { - struct spi_master *master; void __iomem *base_addr; struct clk *hclk; struct clk *mclk; @@ -189,6 +193,9 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) else reg &= ~SUN6I_TFR_CTL_CS_LEVEL; + /* We want to control the chip select manually */ + reg |= SUN6I_TFR_CTL_CS_MANUAL; + sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); } @@ -197,6 +204,39 @@ static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) return SUN6I_MAX_XFER_SIZE - 1; } +static int sun6i_spi_prepare_message(struct spi_master *master, + struct spi_message *msg) +{ + struct spi_device *spi = msg->spi; + struct sun6i_spi *sspi = spi_master_get_devdata(master); + u32 reg; + + /* + * Setup the transfer control register: Chip Select, + * polarities, etc. + */ + reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); + + if (spi->mode & SPI_CPOL) + reg |= SUN6I_TFR_CTL_CPOL; + else + reg &= ~SUN6I_TFR_CTL_CPOL; + + if (spi->mode & SPI_CPHA) + reg |= SUN6I_TFR_CTL_CPHA; + else + reg &= ~SUN6I_TFR_CTL_CPHA; + + if (spi->mode & SPI_LSB_FIRST) + reg |= SUN6I_TFR_CTL_FBS; + else + reg &= ~SUN6I_TFR_CTL_FBS; + + sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); + + return 0; +} + static int sun6i_spi_transfer_one(struct spi_master *master, struct spi_device *spi, struct spi_transfer *tfr) @@ -235,27 +275,8 @@ static int sun6i_spi_transfer_one(struct spi_master *master, (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) | (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS)); - /* - * Setup the transfer control register: Chip Select, - * polarities, etc. - */ - reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); - - if (spi->mode & SPI_CPOL) - reg |= SUN6I_TFR_CTL_CPOL; - else - reg &= ~SUN6I_TFR_CTL_CPOL; - - if (spi->mode & SPI_CPHA) - reg |= SUN6I_TFR_CTL_CPHA; - else - reg &= ~SUN6I_TFR_CTL_CPHA; - - if (spi->mode & SPI_LSB_FIRST) - reg |= SUN6I_TFR_CTL_FBS; - else - reg &= ~SUN6I_TFR_CTL_FBS; + reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); /* * If it's a TX only transfer, we don't want to fill the RX * FIFO with bogus data @@ -265,11 +286,9 @@ static int sun6i_spi_transfer_one(struct spi_master *master, else reg |= SUN6I_TFR_CTL_DHB; - /* We want to control the chip select manually */ - reg |= SUN6I_TFR_CTL_CS_MANUAL; - sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); + /* Ensure that we have a parent clock fast enough */ mclk_rate = clk_get_rate(sspi->mclk); if (mclk_rate < (2 * tfr->speed_hz)) { @@ -442,12 +461,24 @@ static int sun6i_spi_probe(struct platform_device *pdev) struct resource *res; int ret = 0, irq; - master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); + master = spi_alloc_master(&pdev->dev, sizeof(*sspi)); if (!master) { dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); return -ENOMEM; } + master->max_speed_hz = SUN6I_SPI_MAX_SPEED_HZ; + master->min_speed_hz = SUN6I_SPI_MIN_SPEED_HZ; + master->num_chipselect = 4; + master->mode_bits = SUN6I_SPI_MODE_BITS; + master->bits_per_word_mask = SPI_BPW_MASK(8); + master->set_cs = sun6i_spi_set_cs; + master->prepare_message = sun6i_spi_prepare_message; + master->transfer_one = sun6i_spi_transfer_one; + master->max_transfer_size = sun6i_spi_max_transfer_size; + master->dev.of_node = pdev->dev.of_node; + master->auto_runtime_pm = true; + platform_set_drvdata(pdev, master); sspi = spi_master_get_devdata(master); @@ -466,26 +497,14 @@ static int sun6i_spi_probe(struct platform_device *pdev) } ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, - 0, "sun6i-spi", sspi); + 0, dev_name(&pdev->dev), sspi); if (ret) { dev_err(&pdev->dev, "Cannot request IRQ\n"); goto err_free_master; } - sspi->master = master; sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); - master->max_speed_hz = 100 * 1000 * 1000; - master->min_speed_hz = 3 * 1000; - master->set_cs = sun6i_spi_set_cs; - master->transfer_one = sun6i_spi_transfer_one; - master->num_chipselect = 4; - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; - master->bits_per_word_mask = SPI_BPW_MASK(8); - master->dev.of_node = pdev->dev.of_node; - master->auto_runtime_pm = true; - master->max_transfer_size = sun6i_spi_max_transfer_size; - sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); if (IS_ERR(sspi->hclk)) { dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); @@ -525,7 +544,7 @@ static int sun6i_spi_probe(struct platform_device *pdev) ret = devm_spi_register_master(&pdev->dev, master); if (ret) { - dev_err(&pdev->dev, "cannot register SPI master\n"); + dev_err(&pdev->dev, "Couldn't register SPI master\n"); goto err_pm_disable; }