From patchwork Fri May 4 22:03:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 10381749 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 48E6A60159 for ; Fri, 4 May 2018 22:04:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3368B29574 for ; Fri, 4 May 2018 22:04:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2799829586; Fri, 4 May 2018 22:04:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7DE8F29574 for ; Fri, 4 May 2018 22:04:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=ooL4P4r0DrPdR8T3rZN+MTZ9+ft04ZhJmtbCqDjfW6U=; b=uxf VcZ2xmPIv/vbIDxjkV/fx6aytbxF1zEdrcJYCaFaeEwepxyjDvsuU/vyhRzfGR2BhHQdQmLo0VnhT xRFhXcCMSgs9tnxvcdmDZlDESTjU30tqFYyCLhKPsBIoU0ryjy2oxLLQwhv7AnyTY3ci0owZLEXMA ptM2s2xMPCwn+qQp1MXwohGxpVDVXVwjkFL1KHzQT88rIo1dVbbH5kkIZizbREL3zoyPzJ8qPhC/5 vVmcUCZE9UZxWoW9qKmK+pDQl3Wh/yS9Rj2FOlds95fB0HBXMC4cGvlixUHE5mw5WL5sZdyl364Pg whSkuL89lNYv9m8rVhSjiSvNVwguitQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fEiop-0006ra-Va; Fri, 04 May 2018 22:04:47 +0000 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fEiol-0006ql-MX for linux-arm-kernel@lists.infradead.org; Fri, 04 May 2018 22:04:46 +0000 Received: by mail-pg0-x241.google.com with SMTP id l2-v6so16295919pgc.7 for ; Fri, 04 May 2018 15:04:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=E+QHgMGBMrhoKiiTELB7YrZY+AR3lNz2+onvSlosTyE=; b=RAPacjb5XrYvuYZZSr4d+2RRyaWjl1McYlU3nBvzsyjEngcJ1USDP8ZSEcGEDrZtD2 dtQ+STq9Wu7Ii2jI0hGpxVpGc8vwsLsOoPBuu3c3Z38G+yT2htWNCzY4KezuZw1shRYU 5yU1KdSQRzT+cnOQ70hF07aXLIJvfVpDIAilQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=E+QHgMGBMrhoKiiTELB7YrZY+AR3lNz2+onvSlosTyE=; b=D4LgAipX82Kw7j1yrkR860gXTbTK4RaNLgnf1vhOy/g382H0gSarcT9GM/+TnPpuX0 TARkoK1Wv/sbs/Gi8HIUfTohpNxsXtvjTsdLHK42mA8VW2Gj5sUI9w+knvhbPJyYThCL S4fwmgF1G0P8GIPPugBKD8sxpz6iYMqqmZSAapZhob9SLm17hzaJuroNifUkbkt58UBq FxyfJwLh6kyQwXUx27+rpxJojJcWk17/JrO0miCpSHqSvIDM0CgdtH6zxTM+evMl7V8a 0/ntqWhtRDOkJlw73XVaq1TCNHFcTLJgryb1MQAwAkNbdqUcggjwBsJVWqX4sIgy0Lzt Ntdw== X-Gm-Message-State: ALQs6tBfa+ZeZ7CXWK7xAHx2dYJRqJyOFH0JagR687Lye6+y7hHQGCCQ p+32a1Sm+1+/jVOxMLMKWw+FCA== X-Google-Smtp-Source: AB8JxZpNCXYYIw0UkPJG59+KTU2JhdWiFGHeunKN9JVZyIJteAHLR/42zK7sBrtOfLTCLbChaGb/iQ== X-Received: by 2002:a17:902:b492:: with SMTP id y18-v6mr29281816plr.2.1525471472197; Fri, 04 May 2018 15:04:32 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:0:1000:1c10:1976:24c6:964c:adf8]) by smtp.gmail.com with ESMTPSA id o4sm33774444pfg.129.2018.05.04.15.04.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 May 2018 15:04:30 -0700 (PDT) From: Douglas Anderson To: Andy Gross Subject: [PATCH] arm64: dts: qcom: sdm845: Sort nodes in the soc by address Date: Fri, 4 May 2018 15:03:56 -0700 Message-Id: <20180504220356.261711-1-dianders@chromium.org> X-Mailer: git-send-email 2.17.0.441.gb46fe60e1d-goog X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180504_150443_808564_B45BDF68 X-CRM114-Status: GOOD ( 11.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Will Deacon , Douglas Anderson , swboyd@chromium.org, David Brown , Rob Herring , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Bjorn Andersson , linux-soc@vger.kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This is pure-churn and should be a no-op. I'm doing it in the hopes of reducing merge conflicts. When things are sorted in a sane way (and by base address seems sane) then it's less likely that future patches will cause merge conflicts. Signed-off-by: Douglas Anderson Acked-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 152 +++++++++++++-------------- 1 file changed, 76 insertions(+), 76 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 486ace9a9e8b..101350743bd2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -158,32 +158,50 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc 105>, + <&gcc 106>; #address-cells = <1>; #size-cells = <1>; ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x17a00000 0x10000>, /* GICD */ - <0x17a60000 0x100000>; /* GICR * 8 */ - interrupts = ; + status = "disabled"; - gic-its@17a40000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x17a40000 0x20000>; + uart2: serial@a84000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa84000 0x4000>; + clock-names = "se"; + clocks = <&gcc 89>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_uart2_default>; + pinctrl-1 = <&qup_uart2_sleep>; + interrupts = ; status = "disabled"; }; - }; - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sdm845"; - reg = <0x100000 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0xa88000 0x4000>; + clock-names = "se"; + clocks = <&gcc 91>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c10_default>; + pinctrl-1 = <&qup_i2c10_sleep>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; tlmm: pinctrl@3400000 { @@ -224,6 +242,45 @@ }; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = ; + + gic-its@17a40000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x17a40000 0x20000>; + status = "disabled"; + }; + }; + timer@17c90000 { #address-cells = <1>; #size-cells = <1>; @@ -281,62 +338,5 @@ status = "disabled"; }; }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0xc440000 0x1100>, - <0xc600000 0x2000000>, - <0xe600000 0x100000>, - <0xe700000 0xa0000>, - <0xc40a000 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0xac0000 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc 105>, - <&gcc 106>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - uart2: serial@a84000 { - compatible = "qcom,geni-debug-uart"; - reg = <0xa84000 0x4000>; - clock-names = "se"; - clocks = <&gcc 89>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_uart2_default>; - pinctrl-1 = <&qup_uart2_sleep>; - interrupts = ; - status = "disabled"; - }; - - i2c10: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0xa88000 0x4000>; - clock-names = "se"; - clocks = <&gcc 91>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_i2c10_default>; - pinctrl-1 = <&qup_i2c10_sleep>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; }; };