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Mon, 14 May 2018 20:59:56 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:0:1000:1511:bde7:107f:fd5:44c8]) by smtp.gmail.com with ESMTPSA id d62-v6sm17711542pga.29.2018.05.14.20.59.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 May 2018 20:59:55 -0700 (PDT) From: Douglas Anderson To: Andy Gross Subject: [PATCH v2] arm64: dts: qcom: sdm845: Sort nodes in the soc by address Date: Mon, 14 May 2018 20:59:22 -0700 Message-Id: <20180515035922.179060-1-dianders@chromium.org> X-Mailer: git-send-email 2.17.0.441.gb46fe60e1d-goog X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180514_210011_021714_72C1E4CD X-CRM114-Status: GOOD ( 11.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Will Deacon , Douglas Anderson , swboyd@chromium.org, David Brown , Rob Herring , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Bjorn Andersson , linux-soc@vger.kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This is pure-churn and should be a no-op. I'm doing it in the hopes of reducing merge conflicts. When things are sorted in a sane way (and by base address seems sane) then it's less likely that future patches will cause merge conflicts. Signed-off-by: Douglas Anderson Acked-by: Bjorn Andersson --- Changes in v2: - rebase atop tree today arch/arm64/boot/dts/qcom/sdm845.dtsi | 96 ++++++++++++++-------------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 7c85e7c596db..96dd4b2a41d6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -198,6 +198,54 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + tcsr_mutex_regs: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x40000>; + }; + + tlmm: pinctrl@3400000 { + compatible = "qcom,sdm845-pinctrl"; + reg = <0x03400000 0xc00000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + apss_shared: mailbox@17990000 { + compatible = "qcom,sdm845-apss-shared"; + reg = <0x17990000 0x1000>; + #mbox-cells = <1>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #address-cells = <1>; @@ -218,24 +266,6 @@ }; }; - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sdm845"; - reg = <0x100000 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - tlmm: pinctrl@3400000 { - compatible = "qcom,sdm845-pinctrl"; - reg = <0x03400000 0xc00000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - timer@17c90000 { #address-cells = <1>; #size-cells = <1>; @@ -293,35 +323,5 @@ status = "disabled"; }; }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0xc440000 0x1100>, - <0xc600000 0x2000000>, - <0xe600000 0x100000>, - <0xe700000 0xa0000>, - <0xc40a000 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x1f40000 0x40000>; - }; - - apss_shared: mailbox@17990000 { - compatible = "qcom,sdm845-apss-shared"; - reg = <0x17990000 0x1000>; - #mbox-cells = <1>; - }; }; };