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[109.252.91.84]) by smtp.gmail.com with ESMTPSA id m84-v6sm3118543lje.91.2018.06.19.04.02.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jun 2018 04:02:53 -0700 (PDT) From: Dmitry Osipenko To: Russell King , Thierry Reding , Jonathan Hunter Subject: [PATCH v2 1/5] ARM: trusted_foundations: Implement L2 cache initialization callback Date: Tue, 19 Jun 2018 14:00:23 +0300 Message-Id: <20180619110027.16935-2-digetx@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180619110027.16935-1-digetx@gmail.com> References: <20180619110027.16935-1-digetx@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180619_040305_547383_846669AD X-CRM114-Status: GOOD ( 14.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, Peter Geis , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Implement L2 cache initialization firmware callback that should be invoked early in boot to enable cache HW. Signed-off-by: Dmitry Osipenko --- arch/arm/firmware/trusted_foundations.c | 27 +++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index 3fb1b5a1dce9..30df6547020f 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -18,8 +18,13 @@ #include #include #include +#include #include +#define TF_CACHE_MAINT 0xfffff100 + +#define TF_CACHE_INIT 1 + #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 #define TF_CPU_PM 0xfffffffc @@ -63,9 +68,31 @@ static int tf_prepare_idle(void) return 0; } +#ifdef CONFIG_CACHE_L2X0 +static void tf_cache_write_sec(unsigned long val, unsigned int reg) +{ + /* + * The L2X0 cache driver shouldn't invoke a write to a secure registers, + * though it's better to reinsure by printing a warning message. + */ + pr_warn("%s: Ignoring write [0x%x]: 0x%08lx\n", __func__, reg, val); +} + +static int tf_init_cache(void) +{ + outer_cache.write_sec = tf_cache_write_sec; + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_INIT, 0); + + return 0; +} +#endif /* CONFIG_CACHE_L2X0 */ + static const struct firmware_ops trusted_foundations_ops = { .set_cpu_boot_addr = tf_set_cpu_boot_addr, .prepare_idle = tf_prepare_idle, +#ifdef CONFIG_CACHE_L2X0 + .l2x0_init = tf_init_cache, +#endif }; void register_trusted_foundations(struct trusted_foundations_platform_data *pd)