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Wed, 20 Jun 2018 01:37:10 -0700 (PDT) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Subject: [PATCH 3/6] dt-bindings: xilinx_dma: add required xlnx, lengthregwidth property Date: Wed, 20 Jun 2018 10:36:50 +0200 Message-Id: <20180620083653.17010-3-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180620083653.17010-1-andrea.merello@gmail.com> References: <20180620083653.17010-1-andrea.merello@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180620_013722_750670_8A811611 X-CRM114-Status: GOOD ( 11.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrea Merello , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The width of the "length register" cannot be autodetected, and it is now specified with a DT property. Add DOC for it. Signed-off-by: Andrea Merello --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index a2b8bfaec43c..acecdc5d8d47 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -36,6 +36,8 @@ Required properties: Required properties for VDMA: - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. +Required properties for AXI DMA: +- xlnx,lengthregwidth: Should be the width of the length register as configured in h/w. Optional properties: - xlnx,include-sg: Tells configured for Scatter-mode in