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bh=lI/z+yKhhFOkL1kzRd55CKW4Yhq8MBfhB4UVprsjI94=; b=HKKcz6yFY1mCngzeLKqpxuRg/qNFVRccSXWcwmsy7Qz/qh9Kk7RIoVgd3IUlq+UkN0 Zg0+v784ODO0KGCACrDExh8N4jClC9nDmEE2AioJBqJx3+Fz3offh97Sm7eoC7WzXBdX ilctmPfbFSC6c9gRrTBkZOay+FaaIM5nXMIExb6qkFNY3aSS0RN/S0zy2ZrxNb0kLXDQ zUMXgBxzQw0w1jXYyi/+77g4Ep27KxdjNahD+du/zLjUDILCLamyiHrLCQO76x7v1DZ1 ZzmyDCaTQhBwITThfCQaSr4iNhaDMN9M7TbkxkZoI3BohBZSX3a0FhqFkLcnLDXU7tqI ifqQ== X-Gm-Message-State: APt69E0RUT6vnl00IQNsP3JMAVdFmrk9hr4aQCPax6O5u+C+3j1unhde nE7P2IkFg3lksqr2w/R7ZaI= X-Google-Smtp-Source: ADUXVKJErvMGErQUP9yfH+BT3D6axs3H8uzfOmaoU4K80n+ZWHoot/NSvu6Z4O4NxPITPMhc0+kcCw== X-Received: by 2002:a1c:9788:: with SMTP id z130-v6mr5136377wmd.88.1529582309584; Thu, 21 Jun 2018 04:58:29 -0700 (PDT) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id e188-v6sm13779773wmf.21.2018.06.21.04.58.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Jun 2018 04:58:28 -0700 (PDT) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Subject: [PATCH v2 1/5] dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors Date: Thu, 21 Jun 2018 13:58:18 +0200 Message-Id: <20180621115822.20058-1-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180621_045842_366929_26D59413 X-CRM114-Status: GOOD ( 14.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrea Merello , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Whenever a single or cyclic transaction is prepared, the driver could eventually split it over several SG descriptors in order to deal with the HW maximum transfer length. This could end up in DMA operations starting from a misaligned address. This seems fatal for the HW if DRE is not enabled. This patch eventually adjusts the transfer size in order to make sure all operations start from an aligned address. Signed-off-by: Andrea Merello --- Changes in v2: - don't introduce copy_mask field, rather rely on already-esistent copy_align field. Suggested by Radhey Shyam Pandey - reword title --- drivers/dma/xilinx/xilinx_dma.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 27b523530c4a..22d7a6b85e65 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1789,10 +1789,15 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( /* * Calculate the maximum number of bytes to transfer, - * making sure it is less than the hw limit + * making sure it is less than the hw limit and that + * the next chunck start address is aligned */ - copy = min_t(size_t, sg_dma_len(sg) - sg_used, - XILINX_DMA_MAX_TRANS_LEN); + copy = sg_dma_len(sg) - sg_used; + if (copy > XILINX_DMA_MAX_TRANS_LEN && + chan->xdev->common.copy_align) + copy = rounddown(XILINX_DMA_MAX_TRANS_LEN, + (1 << chan->xdev->common.copy_align)); + hw = &segment->hw; /* Fill in the descriptor */ @@ -1894,10 +1899,15 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( /* * Calculate the maximum number of bytes to transfer, - * making sure it is less than the hw limit + * making sure it is less than the hw limit and that + * the next chunck start address is aligned */ - copy = min_t(size_t, period_len - sg_used, - XILINX_DMA_MAX_TRANS_LEN); + copy = period_len - sg_used; + if (copy > XILINX_DMA_MAX_TRANS_LEN && + chan->xdev->common.copy_align) + copy = rounddown(XILINX_DMA_MAX_TRANS_LEN, + (1 << chan->xdev->common.copy_align)); + hw = &segment->hw; xilinx_axidma_buf(chan, hw, buf_addr, sg_used, period_len * i);