From patchwork Mon Jul 2 16:49:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 10502093 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C4A1360284 for ; Mon, 2 Jul 2018 16:49:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AD1EF28D4E for ; Mon, 2 Jul 2018 16:49:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A133E28D52; Mon, 2 Jul 2018 16:49:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E392828D4E for ; Mon, 2 Jul 2018 16:49:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IOxl4Er+4ixmNtUD2yFZiUFXDoqKb97+CYY3B+nNJF4=; b=Wi5PuskVFNg2If Y1VElxLjm0c8YL0N+4Qhg0kAkhBL/5aZ3Dhg8fhkziI44lLBaA51q4SWm0/cE2prulgmfqN0bYnsj K4YiIpwxa4jCrwWkq5GB5D8TSQsqdOuLg39S1TsIylFMlY5zoNDivVqIlpzB5RE9jv1izKjhxv87o AoUbEieR/elrrMFcgqOYy5G4gC5iqxt8SOe7ON/Fy+cVa9tcp7tHMqlmbGg2BMceC/v4RulbkN0kW nlW2idX94R8FIujMKt6+a+9GRfN2fZzXtca/VT8OqI6FuXdSgxQ52hRI88UkGK+937bwXazbJiqLG ufyblMJdYBWgaiuZzQ4w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fa20o-0002gM-1s; Mon, 02 Jul 2018 16:49:14 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fa20j-0002eW-Rw for linux-arm-kernel@lists.infradead.org; Mon, 02 Jul 2018 16:49:11 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 98CA480D; Mon, 2 Jul 2018 09:48:59 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 468303F5BA; Mon, 2 Jul 2018 09:48:59 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 9A1B91AE559D; Mon, 2 Jul 2018 17:49:38 +0100 (BST) Date: Mon, 2 Jul 2018 17:49:38 +0100 From: Will Deacon To: Mathieu Desnoyers Subject: Re: [PATCH 3/3] rseq/selftests: Add support for arm64 Message-ID: <20180702164937.GA23687@arm.com> References: <1529949285-11013-1-git-send-email-will.deacon@arm.com> <1529949285-11013-4-git-send-email-will.deacon@arm.com> <501929863.3051.1529950210436.JavaMail.zimbra@efficios.com> <20180626151427.GF23375@arm.com> <1763491947.3520.1530029512923.JavaMail.zimbra@efficios.com> <20180628164700.GD10751@arm.com> <176714835.9396.1530219040151.JavaMail.zimbra@efficios.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <176714835.9396.1530219040151.JavaMail.zimbra@efficios.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180702_094909_916203_85A7DDA6 X-CRM114-Status: GOOD ( 23.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , peter maydell , Arnd Bergmann , Peter Zijlstra , Catalin Marinas , Boqun Feng , linux-kernel , "Paul E. McKenney" , linux-arm-kernel Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, Jun 28, 2018 at 04:50:40PM -0400, Mathieu Desnoyers wrote: > ----- On Jun 28, 2018, at 12:47 PM, Will Deacon will.deacon@arm.com wrote: > > On Tue, Jun 26, 2018 at 12:11:52PM -0400, Mathieu Desnoyers wrote: > >> ----- On Jun 26, 2018, at 11:14 AM, Will Deacon will.deacon@arm.com wrote: > >> > On Mon, Jun 25, 2018 at 02:10:10PM -0400, Mathieu Desnoyers wrote: > >> >> I notice you are using the instructions > >> >> > >> >> adrp > >> >> add > >> >> str > >> >> > >> >> to implement RSEQ_ASM_STORE_RSEQ_CS(). Did you compare > >> >> performance-wise with an approach using a literal pool > >> >> near the instruction pointer like I did on arm32 ? > >> > > >> > I didn't, no. Do you have a benchmark to hand so I can give this a go? > >> > >> see tools/testing/selftests/rseq/param_test_benchmark --help > >> > >> It's a stripped-down version of param_test, without all the code for > >> delay loops and testing checks. > >> > >> Example use for counter increment with 4 threads, doing 5G counter > >> increments per thread: > >> > >> time ./param_test_benchmark -T i -t 4 -r 5000000000 > > > > Thanks. I ran that on a few arm64 systems I have access to, with three > > configurations of the selftest: > > > > 1. As I posted > > 2. With the abort signature and branch in-lined, so as to avoid the CBNZ > > address limitations in large codebases > > 3. With both the abort handler and the table inlined (i.e. the same thing > > as 32-bit). > > > > There isn't a reliably measurable difference between (1) and (2), but I take > > between 12% and 27% hit between (2) and (3). > > Those results puzzle me. Do you have the actual code snippets of each > implementation nearby ? Sure, I've included the diffs for (2) and (3) below. They both apply on top of my branch at: git://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git rseq Will --->8 diff --git a/tools/testing/selftests/rseq/rseq-arm64.h b/tools/testing/selftests/rseq/rseq-arm64.h index 599788f74137..954f34671ca6 100644 --- a/tools/testing/selftests/rseq/rseq-arm64.h +++ b/tools/testing/selftests/rseq/rseq-arm64.h @@ -104,11 +104,11 @@ do { \ __rseq_str(label) ":\n" #define RSEQ_ASM_DEFINE_ABORT(label, abort_label) \ - " .pushsection __rseq_failure, \"ax\"\n" \ - " .long " __rseq_str(RSEQ_SIG) "\n" \ + " b 222f\n" \ + " .inst " __rseq_str(RSEQ_SIG) "\n" \ __rseq_str(label) ":\n" \ " b %l[" __rseq_str(abort_label) "]\n" \ - " .popsection\n" + "222:\n" #define RSEQ_ASM_OP_STORE(value, var) \ " str %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n" --->8 diff --git a/tools/testing/selftests/rseq/rseq-arm64.h b/tools/testing/selftests/rseq/rseq-arm64.h index 599788f74137..2554aa17acf3 100644 --- a/tools/testing/selftests/rseq/rseq-arm64.h +++ b/tools/testing/selftests/rseq/rseq-arm64.h @@ -80,35 +80,37 @@ do { \ #define RSEQ_ASM_TMP_REG "x15" #define RSEQ_ASM_TMP_REG_2 "x14" -#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \ +#define __RSEQ_ASM_DEFINE_TABLE(version, flags, start_ip, \ post_commit_offset, abort_ip) \ - " .pushsection __rseq_table, \"aw\"\n" \ - " .balign 32\n" \ - __rseq_str(label) ":\n" \ " .long " __rseq_str(version) ", " __rseq_str(flags) "\n" \ " .quad " __rseq_str(start_ip) ", " \ __rseq_str(post_commit_offset) ", " \ - __rseq_str(abort_ip) "\n" \ - " .popsection\n" + __rseq_str(abort_ip) "\n" -#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \ - __RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \ - (post_commit_ip - start_ip), abort_ip) +#define RSEQ_ASM_DEFINE_TABLE(start_ip, post_commit_ip, abort_ip) \ + " .pushsection __rseq_table, \"aw\"\n" \ + " .balign 32\n" \ + __RSEQ_ASM_DEFINE_TABLE(0x0, 0x0, start_ip, \ + (post_commit_ip - start_ip), abort_ip) \ + " .popsection\n" -#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \ +#define RSEQ_ASM_STORE_RSEQ_CS(label, table_label, rseq_cs) \ RSEQ_INJECT_ASM(1) \ - " adrp " RSEQ_ASM_TMP_REG ", " __rseq_str(cs_label) "\n" \ - " add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \ - ", :lo12:" __rseq_str(cs_label) "\n" \ + " adr " RSEQ_ASM_TMP_REG ", " __rseq_str(table_label) "\n" \ " str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(rseq_cs) "]\n" \ __rseq_str(label) ":\n" -#define RSEQ_ASM_DEFINE_ABORT(label, abort_label) \ - " .pushsection __rseq_failure, \"ax\"\n" \ - " .long " __rseq_str(RSEQ_SIG) "\n" \ +#define RSEQ_ASM_DEFINE_ABORT(table_label, start_ip, post_commit_ip, label, \ + abort_label) \ + " b 222f\n" \ + " .balign 32\n" \ + __rseq_str(table_label) ":\n" \ + __RSEQ_ASM_DEFINE_TABLE(0x0, 0x0, start_ip, \ + (post_commit_ip - start_ip), label ## f) \ + " .inst " __rseq_str(RSEQ_SIG) "\n" \ __rseq_str(label) ":\n" \ " b %l[" __rseq_str(abort_label) "]\n" \ - " .popsection\n" + "222:\n" #define RSEQ_ASM_OP_STORE(value, var) \ " str %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n" @@ -181,8 +183,8 @@ int rseq_cmpeqv_storev(intptr_t *v, intptr_t expect, intptr_t newv, int cpu) RSEQ_INJECT_C(9) __asm__ __volatile__ goto ( - RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) - RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_DEFINE_TABLE(1f, 2f, 4f) + RSEQ_ASM_STORE_RSEQ_CS(1, 3f, rseq_cs) RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) RSEQ_INJECT_ASM(3) RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail]) @@ -191,9 +193,9 @@ int rseq_cmpeqv_storev(intptr_t *v, intptr_t expect, intptr_t newv, int cpu) RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, %l[error1]) RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2]) #endif - RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) + RSEQ_ASM_OP_FINAL_STORE(newv, v, 2) RSEQ_INJECT_ASM(5) - RSEQ_ASM_DEFINE_ABORT(4, abort) + RSEQ_ASM_DEFINE_ABORT(3, 1b, 2b, 4, abort) : /* gcc asm goto does not allow outputs */ : [cpu_id] "r" (cpu), [current_cpu_id] "Qo" (__rseq_abi.cpu_id), @@ -230,8 +232,8 @@ int rseq_cmpnev_storeoffp_load(intptr_t *v, intptr_t expectnot, RSEQ_INJECT_C(9) __asm__ __volatile__ goto ( - RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) - RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_DEFINE_TABLE(1f, 2f, 4f) + RSEQ_ASM_STORE_RSEQ_CS(1, 3f, rseq_cs) RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) RSEQ_INJECT_ASM(3) RSEQ_ASM_OP_CMPNE(v, expectnot, %l[cmpfail]) @@ -243,9 +245,9 @@ int rseq_cmpnev_storeoffp_load(intptr_t *v, intptr_t expectnot, RSEQ_ASM_OP_R_LOAD(v) RSEQ_ASM_OP_R_STORE(load) RSEQ_ASM_OP_R_LOAD_OFF(voffp) - RSEQ_ASM_OP_R_FINAL_STORE(v, 3) + RSEQ_ASM_OP_R_FINAL_STORE(v, 2) RSEQ_INJECT_ASM(5) - RSEQ_ASM_DEFINE_ABORT(4, abort) + RSEQ_ASM_DEFINE_ABORT(3, 1b, 2b, 4, abort) : /* gcc asm goto does not allow outputs */ : [cpu_id] "r" (cpu), [current_cpu_id] "Qo" (__rseq_abi.cpu_id), @@ -281,8 +283,8 @@ int rseq_addv(intptr_t *v, intptr_t count, int cpu) RSEQ_INJECT_C(9) __asm__ __volatile__ goto ( - RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) - RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_DEFINE_TABLE(1f, 2f, 4f) + RSEQ_ASM_STORE_RSEQ_CS(1, 3f, rseq_cs) RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) RSEQ_INJECT_ASM(3) #ifdef RSEQ_COMPARE_TWICE @@ -290,9 +292,9 @@ int rseq_addv(intptr_t *v, intptr_t count, int cpu) #endif RSEQ_ASM_OP_R_LOAD(v) RSEQ_ASM_OP_R_ADD(count) - RSEQ_ASM_OP_R_FINAL_STORE(v, 3) + RSEQ_ASM_OP_R_FINAL_STORE(v, 2) RSEQ_INJECT_ASM(4) - RSEQ_ASM_DEFINE_ABORT(4, abort) + RSEQ_ASM_DEFINE_ABORT(3, 1b, 2b, 4, abort) : /* gcc asm goto does not allow outputs */ : [cpu_id] "r" (cpu), [current_cpu_id] "Qo" (__rseq_abi.cpu_id), @@ -324,8 +326,8 @@ int rseq_cmpeqv_trystorev_storev(intptr_t *v, intptr_t expect, RSEQ_INJECT_C(9) __asm__ __volatile__ goto ( - RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) - RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_DEFINE_TABLE(1f, 2f, 4f) + RSEQ_ASM_STORE_RSEQ_CS(1, 3f, rseq_cs) RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) RSEQ_INJECT_ASM(3) RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail]) @@ -336,9 +338,9 @@ int rseq_cmpeqv_trystorev_storev(intptr_t *v, intptr_t expect, #endif RSEQ_ASM_OP_STORE(newv2, v2) RSEQ_INJECT_ASM(5) - RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) + RSEQ_ASM_OP_FINAL_STORE(newv, v, 2) RSEQ_INJECT_ASM(6) - RSEQ_ASM_DEFINE_ABORT(4, abort) + RSEQ_ASM_DEFINE_ABORT(3, 1b, 2b, 4, abort) : /* gcc asm goto does not allow outputs */ : [cpu_id] "r" (cpu), [current_cpu_id] "Qo" (__rseq_abi.cpu_id), @@ -378,8 +380,8 @@ int rseq_cmpeqv_trystorev_storev_release(intptr_t *v, intptr_t expect, RSEQ_INJECT_C(9) __asm__ __volatile__ goto ( - RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) - RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_DEFINE_TABLE(1f, 2f, 4f) + RSEQ_ASM_STORE_RSEQ_CS(1, 3f, rseq_cs) RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) RSEQ_INJECT_ASM(3) RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail]) @@ -390,9 +392,9 @@ int rseq_cmpeqv_trystorev_storev_release(intptr_t *v, intptr_t expect, #endif RSEQ_ASM_OP_STORE(newv2, v2) RSEQ_INJECT_ASM(5) - RSEQ_ASM_OP_FINAL_STORE_RELEASE(newv, v, 3) + RSEQ_ASM_OP_FINAL_STORE_RELEASE(newv, v, 2) RSEQ_INJECT_ASM(6) - RSEQ_ASM_DEFINE_ABORT(4, abort) + RSEQ_ASM_DEFINE_ABORT(3, 1b, 2b, 4, abort) : /* gcc asm goto does not allow outputs */ : [cpu_id] "r" (cpu), [current_cpu_id] "Qo" (__rseq_abi.cpu_id), @@ -432,8 +434,8 @@ int rseq_cmpeqv_cmpeqv_storev(intptr_t *v, intptr_t expect, RSEQ_INJECT_C(9) __asm__ __volatile__ goto ( - RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) - RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_DEFINE_TABLE(1f, 2f, 4f) + RSEQ_ASM_STORE_RSEQ_CS(1, 3f, rseq_cs) RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) RSEQ_INJECT_ASM(3) RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail]) @@ -445,9 +447,9 @@ int rseq_cmpeqv_cmpeqv_storev(intptr_t *v, intptr_t expect, RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2]) RSEQ_ASM_OP_CMPEQ(v2, expect2, %l[error3]) #endif - RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) + RSEQ_ASM_OP_FINAL_STORE(newv, v, 2) RSEQ_INJECT_ASM(6) - RSEQ_ASM_DEFINE_ABORT(4, abort) + RSEQ_ASM_DEFINE_ABORT(3, 1b, 2b, 4, abort) : /* gcc asm goto does not allow outputs */ : [cpu_id] "r" (cpu), [current_cpu_id] "Qo" (__rseq_abi.cpu_id), @@ -489,8 +491,8 @@ int rseq_cmpeqv_trymemcpy_storev(intptr_t *v, intptr_t expect, RSEQ_INJECT_C(9) __asm__ __volatile__ goto ( - RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) - RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_DEFINE_TABLE(1f, 2f, 4f) + RSEQ_ASM_STORE_RSEQ_CS(1, 3f, rseq_cs) RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) RSEQ_INJECT_ASM(3) RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail]) @@ -501,9 +503,9 @@ int rseq_cmpeqv_trymemcpy_storev(intptr_t *v, intptr_t expect, #endif RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) RSEQ_INJECT_ASM(5) - RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) + RSEQ_ASM_OP_FINAL_STORE(newv, v, 2) RSEQ_INJECT_ASM(6) - RSEQ_ASM_DEFINE_ABORT(4, abort) + RSEQ_ASM_DEFINE_ABORT(3, 1b, 2b, 4, abort) : /* gcc asm goto does not allow outputs */ : [cpu_id] "r" (cpu), [current_cpu_id] "Qo" (__rseq_abi.cpu_id), @@ -544,8 +546,8 @@ int rseq_cmpeqv_trymemcpy_storev_release(intptr_t *v, intptr_t expect, RSEQ_INJECT_C(9) __asm__ __volatile__ goto ( - RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) - RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) + RSEQ_ASM_DEFINE_TABLE(1f, 2f, 4f) + RSEQ_ASM_STORE_RSEQ_CS(1, 3f, rseq_cs) RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, 4f) RSEQ_INJECT_ASM(3) RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail]) @@ -556,9 +558,9 @@ int rseq_cmpeqv_trymemcpy_storev_release(intptr_t *v, intptr_t expect, #endif RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) RSEQ_INJECT_ASM(5) - RSEQ_ASM_OP_FINAL_STORE_RELEASE(newv, v, 3) + RSEQ_ASM_OP_FINAL_STORE_RELEASE(newv, v, 2) RSEQ_INJECT_ASM(6) - RSEQ_ASM_DEFINE_ABORT(4, abort) + RSEQ_ASM_DEFINE_ABORT(3, 1b, 2b, 4, abort) : /* gcc asm goto does not allow outputs */ : [cpu_id] "r" (cpu), [current_cpu_id] "Qo" (__rseq_abi.cpu_id),