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Thu, 19 Jul 2018 17:54:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1532022870; bh=RUT5qTtN/rIOQVevWlXDY20IroBTfHYHvQ3ld0GOq3s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lM30SSu6qh0qO6jZXvE689MEMCG1+wev5BHn3u+C1dVj/5+IEoPAf1NJvTR4jc8A1 8LDRHl8gbxC8H9096kqop++HGNShwudsu5to88wpFieeGYPRF/Y9i1GqHmx5j0AbaW fCq1m4lCUFFGUklbYHXAu/3WGoGaGOGRdBrFGOdw= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DF79360B7F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org From: Vivek Gautam To: joro@8bytes.org, robh+dt@kernel.org, robin.murphy@arm.com, will.deacon@arm.com, andy.gross@linaro.org Subject: [PATCH 2/3] dts: arm64/sdm845: Add node for qcom,smmu-v2 Date: Thu, 19 Jul 2018 23:23:55 +0530 Message-Id: <20180719175356.14753-3-vivek.gautam@codeaurora.org> X-Mailer: git-send-email 2.16.1.72.g5be1f00a9a70 In-Reply-To: <20180719175356.14753-1-vivek.gautam@codeaurora.org> References: <20180719175356.14753-1-vivek.gautam@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180719_105432_659830_B9BC2893 X-CRM114-Status: GOOD ( 12.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tfiga@chromium.org, david.brown@linaro.org, iommu@lists.linux-foundation.org, Vivek Gautam , sricharan@codeaurora.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add device node for qcom,smmu-v2 available on sdm845. This smmu is available only to GPU device. Signed-off-by: Vivek Gautam --- One power domain required for this GPU smmu - GPU_CX_GDSC, commented out in the node is coming from gpu clock controller [1]. [1] https://lore.kernel.org/patchwork/cover/962208/ arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 4 ++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 13b50dff440f..969aa76bdceb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -62,3 +62,7 @@ &apps_smmu { status = "okay"; }; + +&gpu_smmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 70ca18ae6cb3..db9f9e84d162 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -980,6 +980,29 @@ cell-index = <0>; }; + gpu_smmu: arm,smmu@5040000 { + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clock-names = "bus", "iface"; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + + /* power-domains = <&gpucc GPU_CX_GDSC>; */ + status = "disabled"; + }; + apps_smmu: arm,smmu@15000000 { compatible = "arm,mmu-500"; reg = <0x15000000 0x80000>;