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Fri, 24 Aug 2018 08:55:16 +0000 From: Peter Rosin To: linux-kernel@vger.kernel.org Subject: [PATCH 1/2] drm/atmel-hlcdc: prefer a higher rate clock as pixel-clock base Date: Fri, 24 Aug 2018 10:55:00 +0200 Message-Id: <20180824085501.9740-2-peda@axentia.se> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180824085501.9740-1-peda@axentia.se> References: <20180824085501.9740-1-peda@axentia.se> MIME-Version: 1.0 X-Originating-IP: [85.226.244.23] X-ClientProxiedBy: VI1PR0701CA0070.eurprd07.prod.outlook.com (2603:10a6:800:5f::32) To AM5PR0201MB2450.eurprd02.prod.outlook.com (2603:10a6:203:35::7) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 40eb9bda-5b0b-4864-3e0a-08d6099f502e X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(7021125)(8989137)(4534165)(7022125)(4603075)(4627221)(201702281549075)(8990107)(7048125)(7024125)(7027125)(7028125)(7023125)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:AM5PR0201MB2450; X-Microsoft-Exchange-Diagnostics: 1; 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E.g. requesting a pixel-clock of 65MHz with a sys_clk of 132MHz results in the divider being set to 3 ending up with 44MHz. By preferring the doubled sys_clk as base, the divider instead ends up as 5 yielding a pixel-clock of 52.8Mhz, which is a definite improvement. While at it, clamp the divider so that it does not overflow in case it gets big. Signed-off-by: Peter Rosin --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index c38a479ada98..71c9cd90d2ae 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -101,18 +101,22 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) (adj->crtc_hdisplay - 1) | ((adj->crtc_vdisplay - 1) << 16)); - cfg = 0; + cfg = ATMEL_HLCDC_CLKSEL; - prate = clk_get_rate(crtc->dc->hlcdc->sys_clk); + prate = 2 * clk_get_rate(crtc->dc->hlcdc->sys_clk); mode_rate = adj->crtc_clock * 1000; - if ((prate / 2) < mode_rate) { - prate *= 2; - cfg |= ATMEL_HLCDC_CLKSEL; - } div = DIV_ROUND_UP(prate, mode_rate); if (div < 2) div = 2; + else if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) { + /* the divider ended up too big, try a lower base rate */ + cfg &= ~ATMEL_HLCDC_CLKSEL; + prate /= 2; + div = DIV_ROUND_UP(prate, mode_rate); + if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) + div = ATMEL_HLCDC_CLKDIV_MASK; + } cfg |= ATMEL_HLCDC_CLKDIV(div);