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Fri, 24 Aug 2018 08:55:22 +0000 From: Peter Rosin To: linux-kernel@vger.kernel.org Subject: [PATCH 2/2] drm/atmel-hlcdc: allow selecting a higher pixel-clock that requested Date: Fri, 24 Aug 2018 10:55:01 +0200 Message-Id: <20180824085501.9740-3-peda@axentia.se> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180824085501.9740-1-peda@axentia.se> References: <20180824085501.9740-1-peda@axentia.se> MIME-Version: 1.0 X-Originating-IP: [85.226.244.23] X-ClientProxiedBy: VI1PR0701CA0070.eurprd07.prod.outlook.com (2603:10a6:800:5f::32) To AM5PR0201MB2450.eurprd02.prod.outlook.com (2603:10a6:203:35::7) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 46304afd-f185-487e-7336-08d6099f53d2 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(7021125)(8989137)(4534165)(7022125)(4603075)(4627221)(201702281549075)(8990107)(7048125)(7024125)(7027125)(7028125)(7023125)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:AM5PR0201MB2450; X-Microsoft-Exchange-Diagnostics: 1; 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I pulled "10 times" as the discriminator out of the hat, and went with that. This is useful, if e.g. the target pixel-clock is 65MHz and the sys_clk is 132MHz. In this case the highest possible pixel-clock lower than the requested 65MHz is 52.8MHz, which is almost 20% off (and outside the spec for the panel). The lowest possible pixel-clock higher than 65MHz is 66MHz, which is a *much* better match, and only 1.5% off. Signed-off-by: Peter Rosin --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 71c9cd90d2ae..0c2717ed4ac6 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -116,6 +116,19 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) div = DIV_ROUND_UP(prate, mode_rate); if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) div = ATMEL_HLCDC_CLKDIV_MASK; + } else { + int div_low = prate / mode_rate; + + if (div_low >= 2 && + ((prate / div_low - mode_rate) < + 10 * (mode_rate - prate / div))) + /* + * At least 10 times better when + * using a higher frequency than + * requested, instead of a lower. + * So, go with that. + */ + div = div_low; } cfg |= ATMEL_HLCDC_CLKDIV(div);