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[109.252.90.13]) by smtp.gmail.com with ESMTPSA id 13-v6sm1420789lfy.87.2018.08.30.11.05.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Aug 2018 11:05:22 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Russell King Subject: [PATCH v3 1/8] ARM: trusted_foundations: Implement L2 cache initialization callback Date: Thu, 30 Aug 2018 21:04:14 +0300 Message-Id: <20180830180421.6415-2-digetx@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180830180421.6415-1-digetx@gmail.com> References: <20180830180421.6415-1-digetx@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180830_110534_550571_237F816C X-CRM114-Status: GOOD ( 14.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Implement L2 cache initialization firmware callback that should be invoked early in boot in order to setup the required outer cache driver callbacks. Signed-off-by: Dmitry Osipenko --- arch/arm/firmware/trusted_foundations.c | 46 +++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index 689e6565abfc..3bf61a5933b9 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -18,8 +18,15 @@ #include #include #include +#include +#include #include +#define TF_CACHE_MAINT 0xfffff100 + +#define TF_CACHE_ENABLE 1 +#define TF_CACHE_DISABLE 2 + #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 #define TF_CPU_PM 0xfffffffc @@ -67,9 +74,48 @@ static int tf_prepare_idle(void) return 0; } +#ifdef CONFIG_CACHE_L2X0 +static void tf_cache_write_sec(unsigned long val, unsigned int reg) +{ + static u32 l2x0_way_mask = 0xff; + static u32 l2x0_aux_ctrl = 0; + + switch (reg) { + case L2X0_AUX_CTRL: + l2x0_aux_ctrl = val; + + if (l2x0_aux_ctrl & BIT(16)) + l2x0_way_mask = 0xffff; + break; + + case L2X0_CTRL: + if (val == L2X0_CTRL_EN) + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_ENABLE, + l2x0_aux_ctrl); + else + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE, + l2x0_way_mask); + break; + + default: + break; + } +} + +static int tf_init_cache(void) +{ + outer_cache.write_sec = tf_cache_write_sec; + + return 0; +} +#endif /* CONFIG_CACHE_L2X0 */ + static const struct firmware_ops trusted_foundations_ops = { .set_cpu_boot_addr = tf_set_cpu_boot_addr, .prepare_idle = tf_prepare_idle, +#ifdef CONFIG_CACHE_L2X0 + .l2x0_init = tf_init_cache, +#endif }; void register_trusted_foundations(struct trusted_foundations_platform_data *pd)