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From: Philipp Zabel
To: linux-media@vger.kernel.org
Subject: [PATCH v3 1/4] dt-bindings: media: Add i.MX Pixel Pipeline binding
Date: Thu, 6 Sep 2018 11:02:12 +0200
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Add DT binding documentation for the Pixel Pipeline (PXP) found on
various NXP i.MX SoCs.
Signed-off-by: Philipp Zabel
Reviewed-by: Rob Herring
---
No changes since v2.
---
.../devicetree/bindings/media/fsl-pxp.txt | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/fsl-pxp.txt
diff --git a/Documentation/devicetree/bindings/media/fsl-pxp.txt b/Documentation/devicetree/bindings/media/fsl-pxp.txt
new file mode 100644
index 000000000000..2477e7f87381
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/fsl-pxp.txt
@@ -0,0 +1,26 @@
+Freescale Pixel Pipeline
+========================
+
+The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
+that supports scaling, colorspace conversion, alpha blending, rotation, and
+pixel conversion via lookup table. Different versions are present on various
+i.MX SoCs from i.MX23 to i.MX7.
+
+Required properties:
+- compatible: should be "fsl,-pxp", where SoC can be one of imx23, imx28,
+ imx6dl, imx6sl, imx6ul, imx6sx, imx6ull, or imx7d.
+- reg: the register base and size for the device registers
+- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
+- clock-names: should be "axi"
+- clocks: the PXP AXI clock
+
+Example:
+
+pxp@21cc000 {
+ compatible = "fsl,imx6ull-pxp";
+ reg = <0x021cc000 0x4000>;
+ interrupts = ,
+ ;
+ clock-names = "axi";
+ clocks = <&clks IMX6UL_CLK_PXP>;
+};