From patchwork Tue Sep 11 08:22:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 10595255 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D62A7920 for ; Tue, 11 Sep 2018 08:26:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C5E7929147 for ; Tue, 11 Sep 2018 08:26:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BA1742914D; Tue, 11 Sep 2018 08:26:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4CA1429147 for ; Tue, 11 Sep 2018 08:26:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dBQSn8OJ44WHI1HE14t5ChzDN3CvXmpRnW0Gb8aDSjU=; b=h7HIA+jdwIPa4Z NiF7o7bsdT8m6CiSmBQMiHfZqzlpwxktm0ZmNltRXVpFYk6IPlmiDIJGkIPQXz6tX7dIrqHDF1SPp 0/xdpJh1jweMXKh67AXcRFHn/igKJSXi9YKodfzRZn1CoYcigZqAxyW7P1gKcEsoZvAl6stjrVYv1 6XAii2+j3EafsQUoUU69gWy3az656JjUl6GU2/sf1+OoH8o9ACt17CDeUGbS6+MG0QfcCVhNbK0am hEbYzyXF/xS62Lj+XfuSXbfpXF/8TG4MdPXjpbWsK1QgvvQMLt/RCcZa2ftNRISUdRJAS/IoZvp57 QR/56T+CuvNI//RAyvXQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fze0Q-0001ZP-Vh; Tue, 11 Sep 2018 08:26:43 +0000 Received: from esa3.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fzdwm-0006tb-OC; Tue, 11 Sep 2018 08:22:59 +0000 X-IronPort-AV: E=Sophos;i="5.53,359,1531810800"; d="scan'208";a="19722857" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 11 Sep 2018 01:22:44 -0700 Received: from localhost.localdomain.com (10.10.76.4) by chn-sv-exch07.mchp-main.com (10.10.76.108) with Microsoft SMTP Server id 14.3.352.0; Tue, 11 Sep 2018 01:22:44 -0700 From: Tudor Ambarus To: , , , , , , , , , , Subject: [PATCH v2 1/3] mtd: spi-nor: add Global Block Unlock support Date: Tue, 11 Sep 2018 11:22:30 +0300 Message-ID: <20180911082232.28678-2-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20180911082232.28678-1-tudor.ambarus@microchip.com> References: <20180911082232.28678-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180911_012256_953930_4C9934ED X-CRM114-Status: GOOD ( 11.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tudor Ambarus Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We can't determine this purely by manufacturer type and it's not autodetectable by anything like SFDP, so make a new flag for it: UNLOCK_GLOBAL_BLOCK. Note that the Global Block Unlock command has different names depending on the manufacturer, but always the same command value: 0x98. Macronix's MX25U12835F names it Gang Block Unlock, Winbound's W25Q128FV names it Global Block Unlock and Microchip's SST26VF064B names it Global Block Protection Unlock. Based on initial work done by Anurag Kumar Vulisha: https://lkml.org/lkml/2015/11/13/307 Signed-off-by: Tudor Ambarus Reviewed-by: Cyrille Pitchen --- drivers/mtd/spi-nor/spi-nor.c | 21 +++++++++++++++++++++ include/linux/mtd/spi-nor.h | 1 + 2 files changed, 22 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index f028277..d3134fd 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -89,6 +89,7 @@ struct flash_info { #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ #define USE_CLSR BIT(14) /* use CLSR command */ +#define UNLOCK_GLOBAL_BLOCK BIT(15) /* Unlock global block protection */ int (*quad_enable)(struct spi_nor *nor); }; @@ -2730,6 +2731,17 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, return 0; } +static int spi_nor_unlock_global_block_protection(struct spi_nor *nor) +{ + int ret; + + write_enable(nor); + ret = nor->write_reg(nor, SPINOR_OP_GBULK, NULL, 0); + if (ret < 0) + return ret; + return spi_nor_wait_till_ready(nor); +} + static int spi_nor_init(struct spi_nor *nor) { int err; @@ -2747,6 +2759,15 @@ static int spi_nor_init(struct spi_nor *nor) spi_nor_wait_till_ready(nor); } + if (nor->info->flags & UNLOCK_GLOBAL_BLOCK) { + err = spi_nor_unlock_global_block_protection(nor); + if (err) { + dev_err(nor->dev, + "Cannot unlock the global block protection\n"); + return err; + } + } + if (nor->quad_enable) { err = nor->quad_enable(nor); if (err) { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index c922e97..09a10fd 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -64,6 +64,7 @@ #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */ +#define SPINOR_OP_GBULK 0x98 /* Global Block Unlock Protection */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */