@@ -222,6 +222,48 @@
clocks = <&sysclk>;
};
+ mmu: iommu@9000000 {
+ compatible = "arm,mmu-500";
+ reg = <0 0x9000000 0 0x400000>;
+ dma-coherent;
+ #global-interrupts = <2>;
+ #iommu-cells = <1>;
+ interrupts = <0 142 4>, /* global secure fault */
+ <0 143 4>, /* combined secure interrupt */
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>,
+ <0 142 4>;
+ };
+
scfg: scfg@1570000 {
compatible = "fsl,ls1043a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;